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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xrt94l43 sonet/sdh oc-12 to 12xds3/e3 mapper november 2006 rev. 1.0.2 general description the xrt94l43 is an sdh to pdh physical layer processor with integrated sonet oc-12 and 12 ds3/e3 framing controller. the xrt94l43 contains an integral sonet framer which provides framing and error accumulation in accordance with ansi/itu- t specifications. for a mu ltiple channel ds3/e3 feature, each channel contains identical elements. the configuration of this device is through internal registers accessible via an 8-bit parallel, memory mapped, microprocessor interface. the sonet/sdh transmit and receive blocks are used to transmit/receive an sts-12/stm-4 signals or compose and decompose 12, sts-1/ds3/e3 signals. the blocks operate at a peak internal clock speed of 77 mhz and support 8-bit internal data paths. the transmit and receive blocks are compliant with both sonet and sdh standards. the xrt94l43 performs all sonet transport and path overhead processing for use in broadband data transport applications. features ? single chip solution for 12 ds3/e3 to sonet/sdh mapping ? generates and terminates sonet section, line and path layers. ? provides sonet frame scrambling and descrambling. ? differential line interfaces ? 8-bit microprocessor interface ? requires +2.5 and +3.3 v power supplies with +5v input tolerance ? -40c to +85c operating temperature range ? available in a 516 ball pbga package applications ? network switches ? concentrators ? frame relay switches ? sonet customer prem ises multiplexers ? network access equipment ? test/monitoring equipment
xrt94l43 2 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper f igure 1. b lock d iagram of the xrt94l43 when c onfigured in sonet m ode tx stm -4 soh processor block tx stm -4 soh processor block stm -4 telecom bus block stm -4 telecom bus block serdes block (primary) serdes block (primary) serdes block (aps) serdes block (aps) clock synthesizer block clock synthesizer block aug # 1 to aug # 2 - 4 microprocessor interface microprocessor interface jtag test port jtag test port rx stm - 4 soh processor block rx stm - 4 soh processor block from aug # 2 - 4 ds3/e3 jitter attenuator block ds3/e3 jitter attenuator block ds3/e3 framer block ds3/e3 framer block ds3/e3 framer block ds3/e3 framer block ds3/e3 framer block ds3/e3 framer block ds3/e3 mapper block ds3/e3 mapper block ds3/e3 mapper block ds3/e3 mapper block ds3/e3 mapper block ds3/e3 mapper block rx tug -3 mapper / vc - 3 poh processor block rx tug -3 mapper / vc - 3 poh processor block tx vc -3 poh processor block tx vc -3 poh processor block tx tug -3 mapper / vc - 3 poh processor block tx tug -3 mapper / vc - 3 poh processor block tx au -4 mapper/vc -4 poh processor block tx au -4 mapper/vc -4 poh processor block rx au -4 mapper/vc -4 poh processor block rx au -4 mapper/vc -4 poh processor block tx stm -4 soh processor block tx stm -4 soh processor block stm -4 telecom bus block stm -4 telecom bus block serdes block (primary) serdes block (primary) serdes block (aps) serdes block (aps) clock synthesizer block clock synthesizer block aug # 1 to aug # 2 - 4 microprocessor interface microprocessor interface jtag test port jtag test port rx stm - 4 soh processor block rx stm - 4 soh processor block from aug # 2 - 4 ds3/e3 jitter attenuator block ds3/e3 jitter attenuator block ds3/e3 jitter attenuator block ds3/e3 jitter attenuator block ds3/e3 framer block ds3/e3 framer block ds3/e3 framer block ds3/e3 framer block ds3/e3 framer block ds3/e3 framer block ds3/e3 framer block ds3/e3 framer block ds3/e3 framer block ds3/e3 framer block ds3/e3 framer block ds3/e3 framer block ds3/e3 mapper block ds3/e3 mapper block ds3/e3 mapper block ds3/e3 mapper block ds3/e3 mapper block ds3/e3 mapper block ds3/e3 mapper block ds3/e3 mapper block ds3/e3 mapper block ds3/e3 mapper block ds3/e3 mapper block ds3/e3 mapper block rx tug -3 mapper / vc - 3 poh processor block rx tug -3 mapper / vc - 3 poh processor block rx tug -3 mapper / vc - 3 poh processor rx tug -3 mapper / vc - 3 poh processor block tx vc -3 poh processor block tx vc -3 poh processor block tx tug -3 mapper / vc - 3 poh processor block tx tug -3 mapper / vc - 3 poh processor block tx vc -3 poh processor block tx vc -3 poh processor block tx tug -3 mapper / vc - 3 poh processor block tx tug -3 mapper / vc - 3 poh processor block tx au -4 mapper/vc -4 poh processor block tx au -4 mapper/vc -4 poh processor block rx au -4 mapper/vc -4 poh processor block rx au -4 mapper/vc -4 poh processor block
xrt94l43 3 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 f igure 2. b lock d iagram of the xrt94l43 when c onfigured in sdh/tug-3 m ode f igure 3. b lock d iagram of the xrt94l43 when c onfigured in sdh/au-3 m ode ds3/ e3 framer bl ock ds3/ e3 framer bl ock rx vc-3 pointer justification bl ock rx vc-3 pointer justification bl ock rx stm-0 vc-3 poh bl ock rx stm-0 vc-3 poh bl ock tx stm-0 vc-3 poh bl ock tx stm-0 vc-3 poh bl ock tx vc-3 pointer justification bl ock tx vc-3 pointer justification bl ock tx stm-0 soh bl ock tx stm-0 soh bl ock rx stm-0 soh bl ock rx stm-0 soh bl ock ds3/ e3 jitter attenuator bl ock ds3/ e3 jitter at t enuat or bl ock ds3/ e3 mapper bl ock ds3/ e3 mapper bl ock tx au-3 mapper/vc-3 poh processor bl ock tx au-3 mapper / vc- 3 poh processor bl ock tx stm-4 soh processor bl ock tx stm-4 soh processor bl ock stm-4 telecom bus bl ock stm-4 telecom bus bl ock serdes bl ock (primary) serdes bl ock (primary) serdes bl ock (aps) serdes bl ock (aps) clock synthesizer block clock synthesizer block channel 1 to channels 2 ? 12 microprocessor interface microprocessor interface jtag test port jtag test port rx au-3 mapper/vc-3 poh processor bl ock rx au-3 mapper/vc-3 poh processor bl ock rx stm-4 soh processor bl ock rx stm-4 soh processor bl ock from channels 2 ? 12 ds3/ e3 framer bl ock ds3/ e3 framer bl ock rx vc-3 pointer justification bl ock rx vc-3 pointer justification bl ock rx stm-0 vc-3 poh bl ock rx stm-0 vc-3 poh bl ock tx stm-0 vc-3 poh bl ock tx stm-0 vc-3 poh bl ock tx vc-3 pointer justification bl ock tx vc-3 pointer justification bl ock tx stm-0 soh bl ock tx stm-0 soh bl ock rx stm-0 soh bl ock rx stm-0 soh bl ock ds3/ e3 jitter attenuator bl ock ds3/ e3 jitter at t enuat or bl ock ds3/ e3 mapper bl ock ds3/ e3 mapper bl ock tx au-3 mapper/vc-3 poh processor bl ock tx au-3 mapper / vc- 3 poh processor bl ock tx stm-4 soh processor bl ock tx stm-4 soh processor bl ock stm-4 telecom bus bl ock stm-4 telecom bus bl ock serdes bl ock (primary) serdes bl ock (primary) serdes bl ock (aps) serdes bl ock (aps) clock synthesizer block clock synthesizer block channel 1 to channels 2 ? 12 microprocessor interface microprocessor interface jtag test port jtag test port rx au-3 mapper/vc-3 poh processor bl ock rx au-3 mapper/vc-3 poh processor bl ock rx stm-4 soh processor bl ock rx stm-4 soh processor bl ock from channels 2 ? 12 ds3/ e3 framer block ds3/e3 framer block rx sts-1 pointer justification bl ock rx sts-1 pointer justification bl ock rx sts-1 poh bl ock rx sts-1 poh bl ock tx sts-1 poh bl ock tx sts-1 poh bl ock tx sts-1 pointer justification bl ock tx sts-1 pointer justification block tx sts-1 toh block tx sts-1 toh bl ock rx sts-1 toh block rx sts-1 toh bl ock ds3/ e3 jitter at t enuat or bl ock ds3/ e3 jitter attenuator bl ock ds3/ e3 mapper block ds3/ e3 mapper block tx sonet poh processor bl ock tx sonet poh processor block tx sts-12 toh processor bl ock tx sts-12 toh processor bl ock sts-12 telecom bus block sts-12 telecom bus block serdes bl ock (primary) serdes bl ock (primary) serdes block (aps) serdes block (aps) clock synthesizer block clock synthesizer block channel 1 to channels 2 ? 12 microprocessor interface microprocessor interface jtag test port jtag test port rx sonet poh processor block rx sonet poh processor bl ock rx sts-12 toh processor block rx sts-12 toh processor bl ock from channels 2 ? 12 ds3/ e3 framer block ds3/e3 framer block rx sts-1 pointer justification bl ock rx sts-1 pointer justification bl ock rx sts-1 poh bl ock rx sts-1 poh bl ock tx sts-1 poh bl ock tx sts-1 poh bl ock tx sts-1 pointer justification bl ock tx sts-1 pointer justification block tx sts-1 toh block tx sts-1 toh bl ock rx sts-1 toh block rx sts-1 toh bl ock ds3/ e3 jitter at t enuat or bl ock ds3/ e3 jitter attenuator bl ock ds3/ e3 mapper block ds3/ e3 mapper block tx sonet poh processor bl ock tx sonet poh processor block tx sts-12 toh processor bl ock tx sts-12 toh processor bl ock sts-12 telecom bus block sts-12 telecom bus block serdes bl ock (primary) serdes bl ock (primary) serdes block (aps) serdes block (aps) clock synthesizer block clock synthesizer block channel 1 to channels 2 ? 12 microprocessor interface microprocessor interface jtag test port jtag test port rx sonet poh processor block rx sonet poh processor bl ock rx sts-12 toh processor block rx sts-12 toh processor bl ock from channels 2 ? 12
xrt94l43 4 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper product features sonet transmitter ? generates and transmits standard sts-12/stm-4 data ? generates and transmits either an stm-4/tug-3 or stm-4/au-3 signals for sdh applications ? conforms to itu-t 1.432, ansi t1 .105 and bellcore gr-253 standards ? performs sonet frame insertion and a ccepts external frame synchronization ? performs optional transmit data scrambling ? permits the user to externally insert their own values for the poh and toh into the outbound sts-12/stm-4 traffic ? generates transmit payload pointer (h1,h2 ) (fixed at 522) with ndf insertion ? inserts a1/a2 with optional error mask ? computes and inserts bip-8 (b 1,b2) with optional error mask ? generates and transmits rei-l and rdi-l either upon software command or automatically based upon errors and defects that are detecte d/declared by the sonet receiver. ? permits the user to transmit the los pattern via software command. ? generates and transmits rdi-p and rei-p either u pon software command or automatically based upon errors and defects that are detecte d/declared by the sonet receiver. ? inserts the fixed-stuff co lumns, calculates and inserts the b3 by te value into each outbound sts-1 spe/vc- 3 or sts-3c spe/vc-4 sonet receiver ? receives and processes standard sts-12/stm-4 signals ? receives and processes either an stm-4/tug- 3 or stm-4/au-3 signal for sdh applications ? permits the user to fully program the b2 byte error-ra te thresholds for declarati on and clearance of the sd and sf defect conditions ? provides section trace buffer with mismat ch detection and invalid message detection ? performs sonet frame synchronization ? supports ndf, positive stuff and negative stuff for pointer processor ? performs receive data de-scrambling ? performs poh and toh interpretation/extraction ? interprets payloa d pointer (h1,h2) ? extracts data communication channels from d1-d3 and d4-d12 ? declares and clears the sef (severely erred frame), lo f (loss of frame) and los (loss of signal) defect conditions ? declares and clears the line ais (ais-l) and the line remote defect indicator (rdi-l) defect conditions ? declares and clears the path - ais (ais-p), loss of pointer (lop-p) and path - unequipped (uneq-p) defect conditions. ? supports either the single-bi t or extended form of rdi-p ? monitors the path signal label and de clares/clears the plm-p defect condition
xrt94l43 5 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ? contains 12 on-chip 64 byte expect ed receive path trace message buffer , in which the user will load in an expected path trace message ? contains 12 on-chip 64 byte actual" receive path trace message buffers, th at will contain the actual received path trace message ? the sonet receiver will use the contents within bo th the expected and actual receive path trace message buffers to either declare or clear the tim-p defect condition ? computes and verifies the b3 by tes within each incomi ng sts-1 spe/vc-3 or sts-3c spe/vc-4 and increments on-chip performance monitoring registers each time it detects b3 byte errors. ? detects and flags line - remote error indicator (rei-l) and path - remote error indicator (rei-p) events, and increments on-chip performance monitoring registers each time it detects rei-l or rei-p events ? computes and verifies both the b1 and b2 bytes wi thin the incoming sts-12/stm-4 data-stream and increments on-chip performance monitoring register s each time it detects b1 or b2 byte errors mapper ? maps ds3 data into/de-maps ds3 data from an sts-1 spe per the requiremen ts in telcordia gr-253- core ? maps ds3/e3 data into/de-maps ds3/e3 data from a vc-3 per itu-t g.707 ? implements au-3 to vc-3 mu ltiplexing and de-multiplexing ds3 receive framer ? offers off-line framing algorithm ? complies with the standards as: bellcore tr-nwt-000499 and tr-nwt-000009 ? supports overhead extraction ? detects and flags lcv (line code violations) and exz (excessive zero events). ? reports and counts febe ? hdlc controller complies with itu-t q.921 lapd protocol ? provides line and local loop-backs ? supports either the m13 or the c-bit parity framing formats ? supports b3zs line decoding which can be user enabled.replaces valid b0v or 00v with 3 zeros ? synchronizes to incoming frame based upon 10 valid f bits followed by 3 consecutive valid m frames, offers optional aic-bit or parity verification before declaration of sync ? detects out of frame (oof) upon 3 or 6 f bits out of 15 f bits in error or 1 or more m bits in 3 of 4 consecutive frames in error ? detects loss of signal (los) upon encountering 180 consec utive 0?s and clears on at least 60 of successive received 1?s.offers optional disable ? detects idle state by checking c-bit in subframe 3 are all zero, x-bits are one and repeating 11001100 payloads. declaration occurs when all the above cond itions persist for 63 m-frames. clears the condition when 63 valid m-frames are received ? detects ais with different algorithm ? computes and verifies p and cp-bits ? validate ferf bits, sets to one when both x-bits are zero and clears when they are one ? detects and validates feac codes upon 8 out of 10 la st identical received codes.invalidates on 3 in 10 mismatch
xrt94l43 6 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ? provides 15-bit prbs lock ds3 transmit framer ? offers following frame generation mechanism: asynchrono us operation, using receive side clock, external framing ? supports either c-bit operation or m13 operation: optional all c bits set to "1" or c-bit parity id bit (c11) toggled in each frame for m13 operation ? provides start of frame control with external pin ? inserts frame overhead bits via external serial port or internal generation ? generates and checks parity ? automatically transmits the ds3 ferf/rei indicator whenever the ds3 receiver declares either the ds3 los, ds3 ais or ds3 oof defect conditions. ? permits the user to control the ds3 f ebe/rei bit-fields via software control, or to automatica lly transmit the febe/rei indicator whenev er the ds3 receiver detects cp-bit or framing (f or m) bit errors ? provides feac channel processing in cluding generation of valid feac pa tterns and transmissions of all 1?s upon programming of idle code ? inserts path maintenance data link through hdlc transmitter which contains the following features: am for storage of entire lapd message selection of message length to 82 or 76 bytes optional frame header generation generation of flag sequences computation and insertion of crc zero stuffing register bits for communi cation with microprocessor interrupt generation upon transmission of message ? los insertion enabled by register bit ? ais insertion enabled by register bit or pin ? idle signal insertion enabled by register bit ? supports b3zs encoding ? generates ais, idle and yellow force alarms ? inserts errors opti onally in the p, f, febe and m bits ? provides 15-bit prbs generator e3 receive framer ? offers off-line framing algorithm ? complies with standards as: itu-t g.751 and g.832 ? provides line code violation detection and excess zero count ? lapd controller complies with itu q.921 lapd protocol ? provides local loop-back ? supports g.751 and g.832 framing formats ? supports hdb3 line decoding which can be user enabled. replaces valid b00v or 000v with 4 zero?s
xrt94l43 7 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ? synchronizes to incoming frame based upon occurrence of two sets of fa1, fa2 with expected separation - g.832 or detection of three consecutiv e frame alignment signals (fas) - g.751 ? detects out of frame (oof) upon 4 consecutive invalid frames ? detects loss of signal (los) upon encountering 32 co nsecutive 0?s and clears on occurrence of 32 bits without a string of 4 0s ? detects ais if 7 or less 0s detected in each of 2 c onsecutive frames and clears if more than seven 0?s detected in each of 2 consecutive frames ? calculation and comparison of bip-8 (g.832) or bip-4 (g.751). bip-4 calculation can be disabled ? supports overhead extraction ? microprocessor access to tr trail trace message - 16 ttb registers (g.832) or service (alarm and nation) bits (g.751) ? detects ma ferf if 3 or 5 consecutive ma msbs are 1and clears if 3 or 5 consecutive ma msbs are 0 (only e3 g.832) ? indicates last validated ferf value and interrupt upon a change in validated ferf value ? extracts payload type (ma) bits and st ores in a register (only e3 g.832) ? extracts timing marker bit and checks for consiste ncy over 3 or 5 consecutive frames (only e3 g.832) ? extracts synchronous status message bits and stores it in register bits when enabled (only g.832) ? overhead output on synchronous serial interface e3 transmit framer ? offers following frame generation mechanism: asynchrono us operation, using receive side clock, external framing ? supports either g.751 or g.832 framing format ? generates and checks parity bip-8 (g.832), bi p-4 (g.751) bip-4 comput ation can be disabled ? inserts data link message through e3 data line channel which contains the following features: insertion into nr or gc byte (programmable through register bit) (e3 g.832 only) insertion into nation bit in case of e3 g.751 when lapd is enabled ram storage of entire lapd message selection of message length to 82 or 76 bytes generation of flag sequences computation and insertion of crc-16 zero stuffing register bits for communication with microprocessors interrupt generation upon complete transmission of message ? los insertion enabled by register bit to force all 0s in the transmit stream ? ais insertion enabled by register bit and/or pin to force all 1?s in the transmit stream ? supports hdb3 encoding enabled by register bit ? inserts frame overhead bits via external serial/nibble po rt (except for fa1,fa2 and em bytes in case of e3 g.832 and fas and bip-4 in case of g.751) or through external overhead interfac e or from configuration register or internal generation ? inserts fa1, fa2, em, tr, ma and gc bytes into g.832 stream or fas service bits and bip4 (if enabled) into g.751 stream
xrt94l43 8 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ? inserts ma,nr,gc and tr (ttb) from microprocesso r accessible registers (service bit for g.751) ? inserts febe in ma upon receipt of em byte errors.programmable through register bit (g.832) ? asserts ferf upon any combination of los,oo f or ais received from receiver (g.832) ? inserts synchronous status messa ge from microprocessor accessible registers, when enabled (g.832) ? error masks for framing bytes, and computed parity (bip-8 in case of g.832 and bip-4 in case of g.751) ? optionally accepts overhead bits (except fa bytes for g.832 and fas bits for g.751) from input interface e3/ds3/sts-1 de-jittering/de-sync circuit ? meets the e3/ds3/sts-1 jitter requirements ? compliant with jitter transfer te mplate outlined in itu g.751 ,g.752,g.755 and gr-499-core ? meets output jitter requirement as specified by etsi tbr24 ? meets the jitter and wander specifications described in t1.105.03b,gr-253 and gr-499 standards ? performs the de-synchronizer function and pointer adjustments for sts-1 to ds3 mapping performance monitoring ? supports line and path performance monitoring ? provides 32-bit saturating counter of oof errors ? provides 32-bit saturating counter lof errors ? provides 32-bit saturating counter of los errors ? provides 32-bit saturating counter of sd errors ? provides 32-bit saturating counter of sf errors ? provides 32-bit saturating counter b3 errors ? provides 32-bit saturating counter of the line rdi, pa th ais,rei-l errors, rei-p errors and bip-8(b1,b2),b3 errors and loss of pointer ? provides 16-bit saturating counter of ds3 framing bit errors, ds3 frame parity errors, line code violations, frame parity (bip) errors, ds3 frame cp bit errors and ds3 far-end block errors ? one second statistics 1. bipolar violations 2. frames with parity errors 3. frames with cp bit errors 4. errored second indication 5. severely errored second indication interrupt, status and test ? provides individually maskable interrupts ? provides one second interrupt generations ? generates interrupts from the following causes: ? ds3 oof status change, los status change, ds 3 ais status, lapd message received, ds3 parity error,ds3 feac validation, ds3 feac removal, ds3 idle status change, febe (e3) change, ds3 ferf change, ds3 format change (aic), lapd end of me ssage transmission and ds3 feac end of message transmission, ds3 framing alignment chan ge, sonet oof status change and cofa ? provides local and remote line loopback
xrt94l43 9 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ? provides sonet remote loopback
xrt94l43 10 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ordering information p art n umber p ackage t ype o perating t emperature r ange xrt94l43ib 516 ball bga -40c to +85c f igure 4. p in o ut of the xrt94l43 (see pin list for pin names and function) top view a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 21 22 19 20 23 24 25 26 1 2 3 4 5 6 7 8 17 18 13 14 15 16 9 10 11 12 a 26 d 23 d 26 ac 1 ac 4 ac 23 ac 26 af 1 af 26 ae 1 ad 1 a1 d1 d4 c1 b1 l4 t4 e1 f1 g1 h1 j1 k1 l1 m1 aa 1 ab 1 u1 v1 w1 y1 n1 p1 r1 t1 l2 t2 l3 t3 l 26 y 26 l 23 t 23 l 24 t 24 l 25 t2 25 xrt94l43 v3 g v1 g g g g g g g g g g g g v2 g v3 v3 v3 v3 v3 v1 v1 v1 v1 v1 v1 v1 v2 v2 v2 v2 v2 v2 v2 l 22 t 22 l 21 t 21 l6 t6 l5 t5
xrt94l43 i sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 table of contents general description ......... ................ ................ ................. .............. .............. .......... 1 features ....................................................................................................................... .......................... 1 applications ........... ................ ................ ................ ................. ................ ............. .......... ....................... 1 f igure 1. b lock d iagram of the xrt94l43 when c onfigured in sonet m ode ..................................................................... 2 f igure 2. b lock d iagram of the xrt94l43 when c onfigured in sdh/tug-3 m ode .............................................................. 3 f igure 3. b lock d iagram of the xrt94l43 when c onfigured in sdh/au-3 m ode ................................................................. 3 product features .............. ................ ................ ................. .............. .............. .......... 4 sonet t ransmitter ............................................................................................................................... ... 4 sonet r eceiver ............................................................................................................................... ......... 4 m apper ............................................................................................................................... ........................ 5 ds3 r eceive f ramer ............................................................................................................................... .. 5 ds3 t ransmit f ramer ............................................................................................................................... 6 e3 r eceive f ramer ............................................................................................................................... ..... 6 e3 t ransmit f ramer ............................................................................................................................... ... 7 e3/ds3/sts-1 d e -j ittering /d e -s ync c ircuit .......................................................................................... 8 p erformance m onitoring ......................................................................................................................... 8 i nterrupt , s tatus and t est ...................................................................................................................... 8 o rdering i nformation ............................................................................................................................. 1 0 f igure 4. p in o ut of the xrt94l43...................................................................................................................... .................... 10 t able of c ontents ............... ................ ................. ................ ................. ................ ........... i pin descriptions - direct addr essing .................. ................ ................. ............ 8 m icroprocessor i nterface ...................................................................................................................... 8 sonet/sdh s erial l ine i nterface p ins ................................................................................................ 13 sts-12/stm-4 t elecom b us i nterface - t ransmit d irection .............................................................. 19 sts-12/stm-4 t elecom b us i nterface - r eceive d irection ................................................................ 22 sonet/sdh o verhead i nterface - t ransmit d irection ...................................................................... 24 sts-3/stm-1 t elecom b us i nterface - t ransmit d irection ................................................................ 33 r x sts-1 toh/poh i nterface ................................................................................................................. 82 sts-3/stm-1 t elecom b us i nterface - r eceive d irection .................................................................. 85 r eceive t ransport o verhead i nterface ............................................................................................. 128 g eneral p urpose i nput /o utput ........................................................................................................... 135 c lock i nputs ............................................................................................................................... ........... 139 b oundary s can ............................................................................................................................... ....... 139 m iscellaneous p ins ............................................................................................................................... 139 p ower s upply p ins ............................................................................................................................... . 140 vdd = 3.3v .................................................................................................................... ........................ 140 vdd (2.5v)..................................................................................................................... ......................... 140 g round ............................................................................................................................... .................... 142 n o c onnects ............................................................................................................................... ........... 142 pin descriptions - indirect a ddressing .............. ................ ................. ........ 144 m icroprocessor i nterface .................................................................................................................. 144 sonet/sdh s erial l ine i nterface p ins .............................................................................................. 146 sts-12/stm-4 t elecom b us i nterface - t ransmit d irection ............................................................ 153 sts-12/stm-4 t elecom b us i nterface - r eceive d irection .............................................................. 156 sonet/sdh o verhead i nterface - t ransmit d irection .................................................................... 158 sts-3/stm-1 t elecom b us i nterface - t ransmit d irection .............................................................. 167 r x sts-1 toh/poh i nterface ............................................................................................................... 219 sts-3/stm-1 t elecom b us i nterface - r eceive d irection ................................................................ 222 r eceive t ransport o verhead i nterface ............................................................................................. 272 g eneral p urpose i nput /o utput ........................................................................................................... 279 c lock i nputs ............................................................................................................................... ........... 287 b oundary s can ............................................................................................................................... ....... 287 m iscellaneous p ins ............................................................................................................................... 287
xrt94l43 ii rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper p ower s upply p ins ............................................................................................................................... 288 vdd = 3.3v.................................................................................................................... ........................ 288 vdd (2.5v) ..................................................................................................................... ........................ 288 g round ............................................................................................................................... ................... 290 n o c onnects ............................................................................................................................... .......... 290 dc electrical characteristics ..... ................ .............. ............... .............. ...... 292 dc c haracteristics for ttl input /cmos output ............................................................................. 292 dc c haracteristics for lvpecl i/o .............. ................ ................. ................ ................ ............. ...... 292 ac electrical characteristics...... ................ .............. ............... .............. ...... 293 1.0 microprocessor interface timi ng for revision d silicon .. ................. ................ ...... 293 1.1 microprocessor interface timi ng - asynchronous intel mode ..... ........... ............ .............. 293 f igure 5. a synchronous m ode 1 - i ntel t ype p rogrammed i/o t iming (w rite c ycle ) ....................................................... 293 f igure 6. a synchronous m ode 1 - i ntel t ype p rogrammed i/o t iming (r ead c ycle )......................................................... 293 t able 1: t iming i nformation for the m icroprocessor i nterface , when configured to operate in the i ntel a synchronous m ode .............................................................................................................................. ........................................... 294 1.2 microprocessor interface timi ng - asynchronous motorola ( 68k) mode ......... ............ 294 f igure 7. a synchronous m ode 2 - m otorola 68k p rogrammed i/o t iming (w rite c ycle ) ................................................ 294 f igure 8. a synchronous m ode 2 - m otorola 68k p rogrammed i/o t iming (r ead c ycle ) ................................................. 295 t able 2: t iming i nformation for the m icroprocessor i nterface when configured to operate in the m otorola (68k) a syn - chronous m ode .............................................................................................................................. .......................... 295 1.3 microprocessor interface timi ng - power pc 403 synchronous mode ........ .............. ...... 296 f igure 9. s ynchronous m ode 3 - ibm p ower pc 403 i nterface t iming (w rite c ycle )....................................................... 296 f igure 10. s ynchronous m ode 3 - ibm p ower pc 403 i nterface t iming (r ead c ycle ) ...................................................... 297 t able 3: t iming i nformation for the m icroprocessor i nterface , when configured to operate in the ibm p ower pc403 m ode 297 1.4 microprocessor interface timing - idt3051/52 mode. .............. .............. ........... ............ .............. 298 f igure 11. s ynchronous m ode 4 - idt3051/52 i nterface t iming (w rite c ycle )................................................................. 298 f igure 12. s ynchronous m ode 4 - idt3051/52 i nterface t iming (r ead c ycle ) .................................................................. 299 t able 4: t iming i nformation for the m icroprocessor i nterface , when configured to operate in the idt3051/52 m ode 299 2.0 sts-12/stm-4 telecom bus interface timing information ............................................. 299 2.1 sts-12/stm-4 telecom bus interface timing information......................................................... 300 2.2 the transmit sts-12/stm-4 telecom bus interface timing ....................................................... 300 f igure 13. w aveforms of the s ignals that are output via the t ransmit sts-12/stm-4 t elecom b us i nterface ......... 300 f igure 14. t iming relationships between the t x sbfp input pin and the t x a_clk output pin within the t ransmit sts-12/stm- 4 t elecom b us i nterface ............................................................................................................................... ......... 301 t able 5: t iming i nformation for the t ransmit sts-12/stm-4 t elecom b us i nterface ..................................................... 301 2.3 the receive sts-12/stm-4 teleco m bus interface timing .......................................................... 301 f igure 15. w aveforms of the s ignals that are i nput via the r eceive sts-12/stm-4 t elecom b us i nterface .............. 302 t able 6: t iming i nformation for the r eceive sts-12/stm-4 t elecom b us i nterface ....................................................... 302 3.0 sts-12/stm-4 pecl interface timing information ............................................................. 303 3.1 the receive sts-12/stm-4 pecl interface timing........................................................................... 3 03 f igure 16. w aveforms of the s ignals that are i nput via the r eceive sts-12/stm-4 pecl i nterface ........................... 303 t able 7: t iming i nformation for the r eceive sts-12/stm-4 pecl i nterface ................................................................... 303 3.2 the transmit sts-12/stm-4 pecl interface block ....................................................................... 304 f igure 17. w aveforms of the t ransmit sts-12/stm-4 pecl i nterface s ignals .............................................................. 304 t able 8: t iming i nformation for the t ransmit sts-12/stm-4 pecl i nterface ................................................................. 304 4.0 ds3/e3/sts-1 liu interface ti ming information.................................................................. 304 4.1 ingress ds3/e3/sts-1 interface ti ming............ .............. .............. .............. ........... ............ ......... ........ 304 f igure 18. w aveforms of the ds3/e3/sts-1 signals that are input to the ds3/e3/sts-1 liu interface in the ingress direc - tion .............................................................................................................................. ............................................. 305 4.2 ingress timing for ds3/ e3 applications ..... .............. .............. .............. .............. ............... ......... ..... 305 t able 9: t iming information for the ingress ds3/ e 3/sts-1 liu interface for ds3/e3 applications when the ds3/e3 framer block has been configured to sample the ds3/e3/sts_1_data_in and ds3/e3/sts_1_neg_in input pins upon the rising edge of ds3/e3/sts_1_clock_in ....................................................................................................... ..... 305 t able 10: t iming i nformation for the i ngress ds3/e3/sts-1 liu i nterface for ds3/e3 a pplications and when the ds3/e3 f ramer b lock has been configured to sample the ds3/e3/sts_1_data_in and ds3/e3/sts_1_neg_in input pins upon the falling edge of ds3/e3/sts_1_clock_in ........................................................................................... 306 4.3 ingress timing for sts-1/stm-0 a pplications ......... .............. .............. .............. ............... .............. 306 t able 11: t iming i nformation for the i ngress ds3/e3/sts-1 liu i nterface for sts-1/stm-0 a pplications ................. 306 4.4 the egress ds3/e3/sts-1 interface timing................................................................................... .... 306 f igure 19. w aveforms of the ds3/e3/sts-1 signals that are output from the ds3/e3/sts-1 liu i nterface ( in the r eceive / e gress d irection ).............................................................................................................................. ...................... 307
xrt94l43 iii sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 4.5 egress timing for ds3/ e3 applications ..... .............. .............. .............. .............. .............. ........... ..... 307 t able 12: t iming i nformation for the e gress ds3/e3/sts-1 liu i nterface for ds3/e3 a pplications and when the ds3/e3 f ramer b lock has been configured to output the outbound ds3/e3 data ( via the ds3/e3/sts_1_data_out and ds3/e3/sts_1_neg_out output pins ) upon the rising edge of ds3/e3/sts_1_clock_out ....................... 307 t able 13: t iming i nformation for the e gress ds3/e3/sts-1 liu i nterface for ds3/e3 a pplications and when the ds3/e3 f ramer b lock has been configured to output the outbound ds3/e3 data ( via the ds3/e3/sts_1_data_out and ds3/e3/sts_1_neg_out output pins ) upon the falling edge of ds3/e3/sts_1_clock_out ..................... 307 4.6 egress timing for sts-1/ stm-0 applications.. .............. .............. .............. .............. .............. ......... . 308 t able 14: t iming i nformation for the e gress ds3/e3/sts-1 liu i nterface for sts-1/stm-0 a pplications .................. 308 5.0 sts-3/stm-1 telecom bus interface timing information ............................................... 308 5.1 sts-3/stm-1 telecom bus interface timing information ........................................................... 308 5.2 the receive sts-3/stm-1 telecom bus interface timing ............................................................ 308 f igure 20. w aveforms of the s ignals that are output via the r eceive sts-3/stm-1 t elecom b us i nterface ............. 309 t able 15: t iming i nformation for the r eceive sts-3/stm-1 t elecom b us i nterface ....................................................... 309 5.3 the transmit sts-3/stm-1 telecom bus interface ti ming.......................................................... 309 f igure 21. w aveforms of the signals that are input via the t ransmit sts-3/stm-1 t elecom b us i nterface .............. 310 t able 16: t iming i nformation for the t ransmit sts-3/stm-1 t elecom b us i nterface ..................................................... 310 6.0 transmit toh overhead input port....................................................................................... 310 6.1 transmit toh overhead input port ........................................................................................... ....... 310 f igure 22. t iming w aveform of the t ransmit toh o verhead i nput p ort .......................................................................... 311 t able 17: t iming i nformation for the t ransmit toh o verhead i nput p ort ....................................................................... 311 7.0 transmit poh overhead input port....................................................................................... 311 7.1 transmit poh overhead input port ........................................................................................... ....... 311 f igure 23. t iming w aveform of the t ransmit poh o verhead i nput p ort .......................................................................... 312 t able 18: t iming i nformation for the t ransmit poh o verhead i nput p ort ....................................................................... 312 8.0 transmit orderwire (e1, f1, e2) byte overhead input port ......................................... 312 8.1 transmit e1, f1, e2 (order-wire ) byte overhead input port ................................................... 312 f igure 24. t iming w aveform of the t ransmit o rder -w ire b yte o verhead i nput p ort .................................................... 313 t able 19: t iming i nformation for the t ransmit o rder -w ire b yte o verhead i nput p ort ................................................. 313 9.0 transmit section dcc insertion input port ...................................................................... 313 9.1 transmit section dcc insertion in put port ............. .............. .............. .............. .............. ............. 313 f igure 25. t iming w aveform of the t ransmit s ection dcc o verhead i nsertion p ort .................................................... 314 t able 20: t iming i nformation for the t ransmit o rder -w ire b yte o verhead i nput p ort ................................................. 314 10.0 transmit line dcc insertion input port ............................................................................ 314 10.1 transmit line dcc insertion input port.................................................................................... .... 314 f igure 26. t iming w aveform of the t ransmit l ine dcc i nsertion i nput p ort ................................................................... 315 t able 21: t iming i nformation for the t ransmit l ine dcc i nsertion i nput p ort ................................................................ 315 11.0 receive toh overhead output port................ .................................................................... 315 11.1 receive toh overhead output port .......................................................................................... ..... 315 f igure 27. t iming w aveform of the r eceive toh o verhead o utput p ort ........................................................................ 316 t able 22: t iming i nformation for the r eceive toh o verhead o utput p ort ..................................................................... 316 12.0 receive poh overhead output port ................................................................................... 316 12.1 receive poh overhead output port .......................................................................................... ..... 316 f igure 28. t iming w aveform of the r eceive poh o verhead o utput p ort ........................................................................ 317 t able 23: t iming i nformation for the r eceive poh o verhead o utput p ort ..................................................................... 317 13.0 receive orderwire (e1, f1, e2) bytes ove rhead output port ................................... 317 13.1 receive e1, f1, e2 (order-wire) byte overhead ou tput port ................................................ 317 f igure 29. t iming w aveform of the r eceive o rder -w ire b yte o verhead o utput p ort ................................................... 318 t able 24: t iming i nformation for the r eceive o rder -w ire b yte o verhead o utput p ort ................................................ 318 14.0 receive section dcc extraction output port ............................................................... 318 14.1 receive section dcc output port ............. .............. .............. .............. .............. ........... ........... ........ 318 f igure 30. t iming w aveform of the r eceive s ection dcc o utput p ort ............................................................................ 319 t able 25: t iming i nformation for the r eceive s ection dcc o utput p ort ......................................................................... 319 15.0 receive line dcc extraction output port ...... ................................................................. 319 15.1 receive line dcc output port .............................................................................................. ............. 319 f igure 31. t iming w aveform of the r eceive l ine dcc o utput p ort .................................................................................. 320 t able 26: t iming i nformation for the r eceive l ine dcc o utput p ort ............................................................................... 320 ordering information....... ................ ................ .............. ............... .............. ........ 321 package dimensions........ ................. ................ ................ ............... .............. ........ 321 r evision h istory ............................................................................................................................... ..... 322
xrt94l43 8 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper pin descriptions - direct addressing microprocessor interface p in # s ignal n ame i/o s ignal t ype d escription u22 pclk i ttl microprocessor interface clock input: this clock input signal is only used if the microprocessor interface has been configured to operate in one of t he synchronous modes (e.g., power pc 403 mode). if the microprocessor interf ace is configured to operate in one of these modes, then it will use this clock signal to do the following. ? to s a m p l e t h e cs , wr /r/ w , a[15:0], d[7:0], rd/ds and dben input pins, and ? to update the state of the d[7:0] and the rdy/dtack output signals. n otes : 1. the microprocessor interface can work with pclk frequencies ranging up to 66mhz. 2. this pin is inactive if the us er has configured the microprocessor interface to operate in either the intel-asynchronous or the motorola-asynchronous modes. in this case, the user should tie this pin to gnd. l25 l23 l22 ptype_0 ptype_1 ptype_2 i ttl microprocessor type select input: these three input pins are used to configure the microprocessor interface block to readily support a wide variety of microprocessor interfaces. the relationship between the settings of these input pins and the corresponding microprocessor interface configuration is presented below. ptype[2:0] microprocessor interface mode 000 intel - asynchronous mode l001 motorola - asynchronous mode (motorola 68k) 010 intel x86 011 intel i960 100 idt3051/52 (mips) 101 power pc 403 mode a23 f24 w21 ae22 a25 h24 ab23 ad15 v26 r24 p26 m24 t26 m22 m25 l26 paddr_0 paddr_1 paddr_2 paddr_3 paddr_4 paddr_5 paddr_6 paddr_7 paddr_8 paddr_9 paddr_10 paddr_11 paddr_12 paddr_13 paddr_14 paddr_15 i ttl address bus input pins (microprocessor interface): these pins permit the microprocessor to identify on-chip registers and buffer/memory locations (within the xrt94l43) whenever it performs read and write operations with the xrt94l43.
xrt94l43 9 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 t22 r22 u24 r21 w26 t25 r25 r26 pdata_0 pdata_1 pdata_2 pdata_3 pdata_4 pdata_5 pdata_6 pdata_7 i/o ttl bi-directional data bus pins (microprocessor interface): these pins are used to drive and rece ive data over the bi-directional data bus,, whenever the microprocessor pe rforms read or write operations with the microprocessor interface of the xrt94l43. y26 wr / r/ w i ttl write strobe/read-write operation identifier: the function of this input pin d epends upon which mode the microproces - sor interface has been configured to operate in. intel-asynchronous mode - wr - write strobe input: if the microprocessor interface is configured to operate in the intel-asyn - chronous mode, then this in put pin functions as the wr (active low write strobe) input signal from the microprocessor. once this active-low signal is asserted, then the input buffers (ass ociated with the bi-directional data bus pin, d[7:0]) will be enabled. th e microprocessor interface will latch the contents on the bi-directional data bus (into the "target" r egister or address location, within the xrt94l43) upon the rising edge of this input pin. motorola-asynchr onous mode - r/ w - read/write operation identifi - cation input pin: if the microprocessor interface is opera ting in the "motorola-asynchronous mode", then this pin is functionally equivalent to the "r/ w " input pin. in the motorola mode, a "read" operation occurs if this pin is held at a logic "1", coincident to a falling edge of the rd/ ds (data strobe) input pin. similarly a write operation occurs if this pin is at a logic "0", coincident to a falling edge of the rd/ ds (data strobe) input pin. power pc 403 mode - r/ w - read/write operatio n identification input: if the microprocessor interface is configured to operate in the power pc 403 mode, then this input pin will func tion as the "read/write operation identification input" pin. anytime the microprocessor interface samples this input signal at a logic low (while also sampling the cs input pin "low") upon the rising edge of pclk, then the microprocessor interface will (upon the very same rising edge of pclk) latch the contents of the address bus (a[15:0]) into the microprocessor interface circ uitry, in preparation for this forthcoming read operation. at some point (later in this read operation) the microprocessor will also assert the dben / oe input pin, and the microprocessor interface will then place the contents of the "target" register (or address location within the xrt94l43) upon the bi-directional data bus pins (d[7:0]), where it can be read by the microprocessor . anytime the microprocessor interface samples this input signal at a logic high (while also sampling the cs input pin a logic "low") upon the rising edge of pclk, then the microprocessor inte rface will (upon the very same rising edge of pclk) latch the contents of the address bus (a[15:0]) into the microprocessor interface circuitry, in preparation for the forthcoming write operation. at some point (later in this write operation) the micro - processor will also assert the rd / ds / we input pin, and the microprocessor interface will then latch the contents of the bi-directional data bus (d[7:0]) into the contents of the "target" register or buffer location (within the xrt94l43). microprocessor interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 10 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper t23 rd/ ds/ we i ttl read strob/data strobe: the function of this input pin d epends upon which mode the microproces - sor interface has been configured to operate in. intel-asynchronous mode - rd - read strobe input: if the microprocessor interface is operating in the intel-asynchronous mode, then this input pin will function as the rd (active low read strobe) input signal from the microprocessor. once this active-low signal is asserted, then the xrt94l43 will place the contents of the addressed reg - ister (or buffer location) on the microprocessor interface bi-directional data bus (d[7:0]). when this signal is negated, then the data bus will be tri- stated. motorola-asynchron ous (68k) mode - ds - data strobe: if the microprocessor interface is operating in the motorola-asynchronous mode, then this input pin will function as the ds (data strobe) input signal. power pc 403 mode - we - write enable input: if the microprocessor interface is operating in the power pc 403 mode, then this input pin will function as the we (write enable) input pin. anytime the microprocessor interface samples this active-low input signal (along with cs and wr /r/ w ) also being asserted (at a logic low level) upon the rising edge of pclk, then the microprocesso r interface will (upon the very same rising edge of pclk) latch the contents on the bi-directional data bus (d[7:0]) into the "target" on-chip register or buffer location within the xrt94l43. r23 pale/pas_l i ttl address latch enable/address strobe: this input pin is used to latch the address (present at the microprocessor interface address bus pins (a[6:0]) into the mapper/framer microprocessor interface block and to i ndicate the start of a re ad or write cycle. this input pin is active-high, in the intel mode and active-low in the motorola mode. v22 pcs_l i ttl chip select input: the user must assert this active lo w signal in order to select the micropro - cessor interface for read and write operations between the micropro - cessor and the xrt94l43 on-chip registers and buffer locations. microprocessor interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 11 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 y25 prdy_l/ dtack / rdy o cmos ready or dtack output: the function of this input pin depends upon which mode the microproces - sor interface has been configured to operate in. intel-asynchronous mode - rdy - ready output: if the microprocessor interface has been configured to operate in the intel- asynchronous mode, then this output pin will function as the "active-low" ready output. during a read or write cycle, th e microprocessor interface block will toggle this output pin to the logic low level, only when it (the microproces - sor interface) is ready to complete or terminate the current read or write cycle. once the microprocessor has determined that this input pin has toggled to the logic "low" level, then it is now safe for it to move on and execute the next read or write cycle. if (during a read or write cycle) th e microprocessor interface block is holding this output pin at a logic "high" level, then the microprocessor is expected to extend this read or write cycle, until it detects this output pin being toggled to the logic low level. motorola-asynchr onous mode - dtack - data transfer acknowledge output if the microprocessor interface has been configured to operate in the motorola-asynchronous mode, then th is output pin will function as the "active-low" dtack output. during a read or write cycle, th e microprocessor interface block will toggle this output pin to the logic low level, only when it (the microproces - sor interface) is ready to complete or terminate the current read or write cycle. once the microprocessor has determined that this input pin has toggled to the logic "low" level, then it is now safe for it to move on and execute the next read or write cycle. if (during a read or write cycle) th e microprocessor interface block is holding this output pin at a logic "high" level, then the microprocessor is expected to extend this read or write cycle, until it detects this output pin being toggled to the logic low level. power pc 403 mode - rdy - ready output: if the microprocessor interface has been configured to operate in the power pc 403 mode, then this output pin w ill function as the "active-high" ready output.during a read or write cycle, the microprocessor interface block will toggle this output pin to the logic high level, only when it (the micro - processor interface) is ready to comple te or terminate the current read or write cycle. once the microprocessor has sampled this signal being at the logic "high" level (upon the rising edge of pclk), then it is now safe for it to move on and execute th e next read or write cycle. if (during a read or write cycle) th e microprocessor interface block is holding this output pin at a logic "low" level, then the microprocessor is expected to extend this read or write cycle, until it samp les this output pin being at the logic low level. n ote : the microprocessor interface will updat e the state of this output pin upon the rising edge of p clk. microprocessor interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 12 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper t21 pdben_l i ttl bi-directional data bus enable input pin: this input pin permits the user to eith er enable or tri-state the bi-directional data bus pins (d[7:0]), as described below. setting this input pin "low" enables the bi-directional data bus. setting this input "high" tri-states the bi-directional data bus. u25 pblast_l i ttl last burst transfer indicator input pin: if the microprocessor interface is operati ng in the intel-i960 mode, then this input pin is used to indicate (to the microprocessor interfac e block) that the current data transfer is the last data transfer within the current burst opera - tion. the microprocessor should assert this input pin (by toggling it "low") in order to denote that the current r ead or write operation (within a burst operation) is the last oper ation of this burst operation. n ote : if the user has configured the mi croprocessor interface to operate in the intel-asynchronous, the motorola-asynchronous or the power pc 403 mode, then he/she should tie this input pin to gnd. ac26 pint_l o cmos interrupt request output: this active-low, active-low output signal will be asserted when the xrt94l43 is requesting interrupt serv ice from the microprocessor. this output pin should typically be connect ed to the interrupt request input of the microprocessor. l24 reset_l i ttl reset input: when this active-low signal is asserted, the xrt94l43 will be asynchro - nously reset. when this occurs, all out puts will be tri-stated and all on-chip registers will be reset to their default values. m26 full_addr_ sel i ttl full address select input pin:this input pin, along with "direct_add_sel" (pin m23) must both be pulled "high" in order to configure the microprocessor interface block to operate in the "full address" mode.if the microprocessor inte rface is configured to operate in the "full address" mode, then it will then provide a 16-bit address bus (which is sufficient to "directly address" all of the on-chip registers. m23 direct_add _sel i ttl direct address select input pin:this input pin, along with "full_addr_sel" (pin m26) must both be pulled "high" in order to con - figure the microprocessor interface block to operate in the "full address" mode.if the microprocessor interface is configured to operate in the "full address" mode, then it will then provi de a 16-bit address bus (which is suf - ficient to "directly address" all of the on-chip registers. microprocessor interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 13 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 sonet/sdh serial line interface pins p in # s ignal n ame i/o s ignal t ype d escription m5 rxl_clkl_p i lvpecl receive sts-12/stm-4 clock - positive polarity pecl input: this input pin, along with rxl_clkl_n functions as the recov - ered clock input, from a system back-plane or an optical trans - ceiver. the receive sts-12/stm-4 interface block will sample the data, applied at the rxldata_p/rxldata_n input pins, upon the rising edge of this signal. n ote : for aps (automatic protection switching) purposes, this input pin, along with rxl_clkl_n functions as the primary receive clock input port. l5 rxl_clkl_n i lvpecl receive sts-12/stm-4 clock - ne gative polarity pecl input: this input pin, along with rxl_clkl_p functions as the recov - ered clock input, from a system back-plane or an optical trans - ceiver. the receiver sts-12/stm-4 interface block will sample the data applied at the rxldata_p/rxldata_n input pins, upon the falling edge of this signal. n ote : for aps (automatic protection switching) purposes, this input pin, along with rxl_ clkl_p functions as the primary receive clock input port. k2 rxl_clkl_r_p i lvpecl receive sts-12/stm-4 clock - po sitive polarity pecl input - redundant port: this input pin, along with rxl_clkl_r_n functions as the recov - ered clock input, from a system back-plane or an optical trans - ceiver. the receive sts-12/stm-4 interface block will sample the data, applied at the rxldata_p/rxldata_n input pins, upon the rising edge of this signal. n ote : for aps (automatic protection switching) purposes, this input pin, along with rxl_c lkl_r_n functions as the redundant receive clock input port. k1 rxl_clkl_r_n i lvpecl receive sts-12/stm-4 clock - ne gative polarity pecl input - redundant port: this input pin, along with rxl_clkl_p functions as the recov - ered clock input, from a system back-plane or an optical trans - ceiver. the receiver sts-12/stm-4 interface block will sample the data applied at the rxldata_p/rxldata_n input pins, upon the falling edge of this signal. n ote : for aps (automatic protection switching) purposes, this input pin, along with rxl_clkl_r_ p functions as the redundant receive clock input port. k4 rxl_data_p i lvpecl receive sts-12/stm-4 data - positive polarity pecl input: this input pin, along with rxl_data_n functions as the recov - ered data input, from a system back-plane or an optical trans - ceiver. the receive sts-12/stm-4 interface block will sample the data applied to these input pins, upon the rising edge of the rxl_clkl_p (and the falling edge of the rxl_clkl_n) signals. n ote : for aps (automatic protection switching) purposes, this input pin, along with rx l_data_n functions as the primary receive data input port.
xrt94l43 14 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper l4 rxl_data_n i lvpecl receive sts-12/stm-4 data - ne gative polari ty pecl input: this input pin, along with rxl_data_p functions as the recov - ered data input, from a system back-plane or an optical trans - ceiver. the receive sts-12/stm-4 interface block will sample the data applied to these input pins, upon the rising edge of the rxl_clkl_p (and the falling edge of the rxl_clkl_n) signals. n ote : for aps (automatic protection switching) purposes, this input pin, along with rxl_da ta_p functions as the primary receive data input port. k3 rxl_data_r_p i lvpecl receive sts-12/stm-4 data - positive polarity pecl input - redundant port: this input pin, along with rxl_data_r_n functions as the recov - ered data input, from a system back-plane or an optical trans - ceiver. the receive sts-12/stm-4 interface block will sample the data applied to these input pins, upon the rising edge of the rxl_clkl_r_p (and the falling edge of the rxl_clkl_r_n) sig - nals. n ote : for aps (automatic protection switching) purposes, this input pin, along with rxl_data_r_n functions as the redundant receive data input port. l3 rxl_data_r_n i lvpecl receive sts-12/stm-4 data - ne gative polarity pecl input - redundant port: this input pin, along with rxl_d ata_r_p functions as the recov - ered data input, from a system back-plane or an optical trans - ceiver. the receive sts-12/stm-4 interface block will sample the data applied to these input pins, upon the rising edge of the rxl_clkl_r_p (and the falling edge of the rxl_clkl_r_n) sig - nals. n ote : for aps (automatic protection switching) purposes, this input pin, along with rxl_data_r_n functions as the redundant receive data input port. t3 txl_clki_p i lvpecl transmit reference clock - positive polarity pecl input: this input pin, along with txl_clki_n can be configured to func - tion as the timing source for the sts-12/stm-4 transmit interface block. if these two input pins are configured to function as the timing source, then a 622.08mhz clock signal must be applied to these input pins in the form of a pecl signal. these two inputs can be configured to function as the timi ng source by writing the appropri - ate data into the interface cont rol register - by te 2 (indirect address = 0x00, 0x31), (direct address = 0x0131). sonet/sdh serial line interface pins p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 15 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 t4 txl_clki_n i lvpecl transmit reference clock - negative polarity pecl input: this input pin, along with txl_clki_p can be configured to func - tion as the timing source for the sts-12/stm-4 transmit interface block. if these two input pins are configured to function as the timing source, then a 622.08mhz clock signal must be applied to these input pins in the form of a pecl signal. these two inputs can be configured to function as the timi ng source by writing the appropri - ate data into the interface cont rol register - byte 2 (indirect address = 0x00, 0x31), (direct address = 0x0131). n1 txl_data_p o lvpecl transmit sts-12/stm-4 data - po sitive polarity pecl output: this output pin, along with txl_da ta_n functions as the transmit data output, to the system back-plane (for transmission to some other system board) or an optical transceiver (for transmission to remote terminal equipment). for high-speed back-plane applications, it should noted that data is output from these output pins upon the rising/falling edge of txl_clko_p/txl_clko_n). n ote : for aps (automatic protection switching) purposes, this output pin, along with tx l_data_n functions as the primary transmit data output port. n2 txl_data_n o lvpecl transmit sts-12/stm-4 data - negative polarity pecl output: this output pin, along with txl_ data_p functions as the transmit data output, to the system back-plane (for transmission to some other system board) or an optical transceiver (for transmission to remote terminal equipment). for high-speed back-plane applications, it should noted that data is output from these output pins upon the rising/falling edge of txl_clko_p/txl_clko_n). n ote : for aps (automatic protection switching) purposes, this output pin, along with txl_data_p functions as the primary transmit data output port. p1 txl_data_r_p o lvpecl transmit sts-12/stm-4 data - po sitive polarity pecl output - redundant port: this output pin, along with txl_data_r_n functions as the transmit data output, to the syst em back-plane (for transmission to some other system board) or an optical transceiver (for trans - mission to remote terminal equipment). for high-speed back-plane applications, it should noted that data is output from these output pins upon the rising/falling edge of txl_clko_r_p/txl_clko_r_n). n ote : for aps (automatic protection switching) purposes, this output pin, along with tx l_data_n functions as the redundant transmit data output port. sonet/sdh serial line interface pins p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 16 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper p2 txl_data_r_n o lvpecl transmit sts-12/stm-4 data - ne gative polarity pecl output - redundant port: this output pin, along with txl_data_r_p functions as the trans - mit data output, to the system back-plane (for transmission to some other system board) or an optical transceiver (for transmis - sion to remote terminal equipment). for high-speed back-plane applications, it should noted that data is output from these output pins upon the rising/falling edge of txl_clko_r_p/txl_clko_r_n). n ote : for aps (automatic protection switching) purposes, this output pin, along with txl_ data_r_p functions as the redundant transmit data output port. m1 txl_clko_p o lvpecl transmit sts-12/stm-4 clock - positive polarity pecl output: this output pin, along with txl_clko_n functions as the transmit clock output signal. these output pins are typically used in high- speed back-plane applications. in this case, outbound sts-12/ stm-4 data is output via the txl_data_p/txl_data_n output pins upon the rising edge of this clock signal. n ote : for aps (automatic protection switching) purposes, this output pin, along with txl_clko_n functions as the primary transmit output clock signal. m2 txl_clko_n o lvpecl transmit sts-12/stm-4 clock - negative polarity pecl out - put: this output pin, along with txlclko_p functions as the transmit clock output signal. these output pins are typically used in high- speed back-plane applications. in this case, outbound sts-12/ stm-4 data is output via the txl_data_p/txl_data_n output pins upon the falling edge of this clock signal. n ote : for aps (automatic protection switching) purposes, this output pin, along with txl_clko_n functions as the primary transmit output clock signal. r1 txl_clko_r_p o lvpecl transmit sts-12/stm-4 clock - positive polarity pecl output - redundant port: this output pin, along with txl_clko_r_n functions as the transmit clock output signal. these output pins are typically used in high-speed back-plane applications. in this case, outbound sts-12/stm-4 data is output via the txl_data_r_p/ txl_data_r_n output pins upon the rising edge of this clock sig - nal. n ote : for aps (automatic protection switching) purposes, this output pin, along with txl_ clko_r_n functions as the redundant transmit output clock signal. sonet/sdh serial line interface pins p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 17 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 r2 txl_clko_r_n o lvpecl transmit sts-12/stm-4 clock - negative polarity pecl output - redundant port: this output pin, along with txl_clko_r_p functions as the transmit clock output signal. these output pins are typically used in high-speed back-plane applications. in this case, outbound sts-12/stm-4 data is output via the txl_data_r_p/ txl_data_r_n output pins upon the rising edge of this clock sig - nal. for aps (automatic protection sw itching) purposes, this output pin, along with txl_clko_r_p functions as the redundant transmit output clock signal. r4 refclk i ttl 77.76mhz or 622.08mhz clock synthesizer reference clock input pin: the function of this input pin depends upon whether or not the transmit sts-12/stm-4 clock synthesizer block is enabled. if clock synthesizer is enabled. if the transmit sts-12/stsm-4 clock synthesizer block is to be used to generate the 77.76mhz and /or 622.08mhz clock signal for the sts-12/stm-4 block, then a clo ck signal of either of the follow - ing frequencies, must be applied to this input pin. ? 12.96mhz ? 19.44mhz ? 51.84 mhz ? 77.76 mhz afterwards, the appropriate data needs to be written into the inter - face control register - byte 2 (indirect address = 0x00, 0x31), (direct address = 0x0131) in order to; (1) configure the clock synthesizer block to accept any of the above-mentioned signals and gener ate a 77.76mhz or 622.08mhz clock signal, (2) to configure the clock synthe sizer to function as the clock source for the sts-12/stm-4 block. if clock synthesizer is not enabled: if the transmit sts-12/stsm-4 clock synthesizer block is not to be used to generate the 77.76mhz and/or 622.08mhz clock signal for the sts-12/stm-4 block, then a 77.76mhz clock signal must be applied to this input pin. af6 los i ttl loss of optical carrier input - primary: the loss of carrier output (from the optical transceiver) should be connected to this input pin. if this input pin is pulled "high", then the primary receive sts-12 toh processor block will declare a loss of optical carrier condi - tion. n ote : this input pin is only active if the primary port is active. this input pin is inactive if t he redundant port is active. sonet/sdh serial line interface pins p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 18 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ae6 los-r i ttl loss of optical carrier input - redundant: the loss of carrier output (from the optical transceiver) should be connected to this input pin. if this input pin is pulled "high", then the redundant receive sts- 12 toh processor block will declare a loss of optical carrier con - dition. n ote : this input pin is only active if the redundant port is active. this input pin is inactive if the primary port is active. ab7 exswitch o cmos external (aps) switch output pin: this output pin can be used to permit the xrt94l43 to perform aps externally. specifically, this output pin can be connected to some circuitry that permits the re-direction of sts-12/stm-4 traffic, should an aps event be needed. n ote : this output pin is disabled if the exswitchdis input pin number ab6 is pulled "high". ab6 exswitchdis i ttl external (aps) switch disable: this input pin permits the user to configure the xrt94l43 to per - form line aps switching internally or externally. 0 - configures the xrt94l43 to perform aps externally. in this mode, the xrt94l43 will execute an aps by toggling the state of the "exswitch" output pin. 1 - configures the xrt94l43 to perform aps internally. in this mode, each of the 12 receive sonet poh processor blocks (within the xrt94l43) will interna lly switch from processing the incoming sts-1 spe data from the "primary" receive sts-12 toh processor block, to now pr ocessing the incoming sts-1 spe data from the "redundant" receive sts-12 toh processor block (or vice-versa). sonet/sdh serial line interface pins p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 19 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 sts-12/stm-4 telecom bus inte rface - transmit direction p in # s ignal n ame i/o s ignal t ype d escription g2 txa_clk o cmos sts-12/stm-4 transmit telecom bus clock signal: this output clock signal functions as the clock source for the sts-12/ stm-4 transmit telecom bus. all output signals (on the transmit sts-12/stm-4 telecom bus) are updat ed upon the rising edge of this clock signal. this clock signal operates at 77.76mhz and is derived from the trans - mit clock synthesizer block. j1 txa_c1j1 o cmos sts-12/stm-4 transmit telecom bus - c1/j1 byte phase indicator output signal: this output pin pulses "high" under the following two conditions. 1. whenever the c1 byte is being output via the txa_ d[7:0] output, and 2. whenever the j1 byte is being output via the txa_ d[7:0] output. n otes : 1. the sts-12/stm-4 transmit telecom bus will indicate that it is transmitting the c1 byte (via the txa_d[7:0] output pins), by pulsing this output pin "high" (for one period of txa_clk) and keeping the txa_pl output pin pulled "low". 2. the sts-12/stm-4 transmit telecom bus will indicate that it is transmitting the j1 byte (via the txa_d[7:0] output pins), by pulsing this output pin "high" (for one period of txa_clk) while the txa_pl output pin is pulled "high". 3. this output pin is only acti ve if the sts-12/stm-4 telecom bus is enabled. j3 txa_alarm o cmos transmit sts-12/stm-4 telecom bus - alarm indicator output sig - nal: this output pin pulses "high", corresponding to any sts-1 signal (that is being output via the txa_d[7:0] output pins) is carrying the ais-p indicator. this output pin is "low" for all other conditions. h1 txa_dp o cmos sts-12/stm-4 transmit teleco m bus - parity output pin: this output pin can be configured to function as one of the following. 1. the even or odd parity value of the bits which are output via the txa_d[7:0] output pins. 2. the even or odd parity value of the bits which are being output via the txa_d[7:0] output pins and the states of the txa_pl and txa_c1j1 output pins. n ote : any one of these configuratio n selections can be made by writing the appropriate value into the telecom bus control register (indirect address = 0x00, 0x37), (direct address = 0x0137)..
xrt94l43 20 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper k5 txsbfp i ttl telecom bus sync reference input: if either the sts-12/stm-4 or any of the sts-3/stm-1 telecom bus interfaces are enabled, then an 8k hz pulse must be applied to this input pin. if the sts-12/stm-4 telecom bus interface is enabled: the transmit sts-12/stm-4 telecom bus interface will begin trans - mitting the very first byte of given sts-12 or stm-4 frame, upon sens - ing a rising edge (of the 8khz signal) at this input pin. if any of the sts-3/stm-1 telecom bus interfaces are enabled: the receive sts-3/stm-1 telecom bu s interfaces will begin transmit - ting the very first byte of a giv en sts-3 or stm-1 frame, upon sensing a rising edge (of the 8khz signal) at this input pin. n ote : if none of the telecom bus interfaces are used, then this pin should be tied to gnd. n otes : 1. 1.if this input pin is tied to gnd, then the transmit sts-12 toh processor block will generate its outbound sts-12/ stm-4 frames asynchronously with respect to any input signal. 2. this input signal must be synch ronized with the signal that is supplied to the refclk input pin. failure to insure this will result in bit errors being generated within the outbound sts- 12/stm-4 signal. 3. an 8khz pulse must be applied to this input pin, that has a width of approximately 12.8ns (one 77.76mhz clock period). do not apply a 50% duty cycle 8k hz signal to this input pin. sts-12/stm-4 telecom bus inte rface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 21 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 f3 txa_pl o cmos sts-12/stm-4 transmit telecom bu s - payload data indicator sig - nal: this output pin indicates whether or not toh (transmit overhead) bytes are being output via th e txa_d[7:0] output pins. this output pin is pulled "low" for the duration that the sts-12/stm-4 transmit telecom bus is transmitting a transport overhead byte via the txa_d[7:0] output pins. conversely, this output pin is pull ed "high" for the duration that the sts-12/stm-4 transmit telecom bus is transmitting something other than a transport overhead (e.g., the poh or sts-1/sts-3c spe bytes) byte via the t xa_d[7:0] output pins. g1 j5 j2 h5 e1 f2 f1 e3 txa_d0 txa_d1 txa_d2 txa_d3 txa_d4 txa_d5 txa_d6 txa_d7 o cmos sts-12/stm-4 transmit telecom bus - transmit output data bus pins: these 8 output pins function as the "sts-12/stm-4 transmit telecom bus" transmit output data bus. if the sts-12/stm-4 telecom bus interface is enabled, then all sts- 12/stm-4 data is output via these pins (in a byte-wide manner), upon the rising edge of the txa_clk output pin. n otes : 1. the pin txa_d7 will output the msb (most significant bit) of each byte that is output via the transmit sts-12/stm-4 telecom bus interface. 2. the pin txa_d0 will output the lsb (least significant bit) of each byte that is output via the transmit sts-12/stm-4 telecom bus interface. sts-12/stm-4 telecom bus inte rface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 22 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper sts-12/stm-4 telecom bus interface - receive direction p in # s ignal n ame i/o s ignal t ype d escription v4 rxd_clk i ttl receive sts-12/stm-4 telecom bus interface - clock input signal: this input clock signal functions as the clock source for the receive sts- 12/stm-4 telecom bus interface. all receive sts-12/stm-4 telecom bus interface input signals are sampled upon the rising edge of this input clock signal. this clock signal should operate at 77.76mhz. n ote : this input pin is only used if the sts-12/stm-4 telecom bus has been enabled. it should be tied to gnd otherwise. u5 rxd_pl i ttl receive sts-12/stm-4 telecom bus interface - payload indicator sig - nal: this input pin indicates whether or not sts- 1/sts-3c spe bytes are being input via the rxd_d[7:0] input pins. this input pin should be pulled "high" coincident to whenever the receive sts-12/stm-4 telecom bus interface block is receiving sts-1/sts-3c spe data bytes via the rx d_d[7:0] i nput pins. conversely, this input pin should be pulled "low" coincident to whenever the receive sts-12/stm-4 telecom bus interface block is receiving something other th an an sts-1/sts-3c spe byte (e.g., a toh byte) via the rxd_d[7:0] input pins. n ote : the user should tie this pin to gnd if the sts-12/stm-4 telecom bus interface is configured to operate in the "re-phase on" mode or is disabled. v2 rxd_c1j1 i ttl sts-12/stm-4 receive telecom bus c1/j1 byte phase indicator input signal: this input pin should be pulsed "high" during both of the following condi - tions. 1. whenever the c1 byte is being input to the receive sts-12/stm-4 telecom bus interface - data bus input pins (rxd_d[7:0]). 2. whenever the j1 byte is being input to the receive sts-12/stm-4 telecom bus telecom bus interface -data bus input pins (rxd_d[7:0]). this input pin should be pulled "low" for all other times. n ote : tie this pin to gnd if the sts-12/stm-4 telecom bus is not enabled.
xrt94l43 23 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 u4 rxd_dp i ttl sts-12/stm-4 receive telecom bus - parity input pin: this input pin can be configured to function as one of the following. 1. the even or odd parity value of the bits which are input via the rxd_d[7:0] input pins. 2. the even or odd parity value of the bits which are being input via the rxd_d[7:0] input and the stat es of the rxd_pl and rxd_c1j1 input pins. the receive sts-12/stm-4 telecom bus interface will use this pin to compute and verify the parity withi n the incoming sts-12/stm-4 data- stream. n otes : 1. any one of these configuration se lections can be made by writing the appropriate value into the telecom bus control register (indirect address = 0x00, 0x37, direct address = 0x0137. 2. tie this pin to gnd if the sts-12/stm-4 telecom bus interface is configured to operate in the re-p hase on mode or is disabled. t2 rxd_alarm i ttl receive sts-12/stm-4 telecom bus - alarm indicator input: this input pin pulses "high" corresponding to any sts-1 signal that is car - rying the ais-p indicator. more specifically, this input pin will be pulsed "high" coincident to when - ever a byte, corresponding to given sts- 1 signal (that is carrying the ais-p indicator) is being placed on the receive sts-12/stm-4 telecom bus - data bus input pins (rxd_d[7:0]). this input pin should be pulled "low" at all other times. n otes : 1. if the rxd_alarm input signal pulses "high" for any given sts-1 signal (within the incoming sts-12), then the xrt94l43 will automatically declare the ais-p defect for that particular sts-1 channel. 2. tie this pin to gnd if the sts-12/stm-4 telecom bus interface has been cofigured to operate in the re-phase on mode or is disbled. u3 v3 u2 t1 v5 u1 w1 v1 rxd_d0 rxd_d1 rxd_d2 rxd_d3 rxd_d4 rxd_d5 rxd_d6 rxd_d7 i ttl receive sts-12/stm-4 receive telecom bus - receive input data bus pins: these 8 input pins function as the "receive sts-12/stm4 receive tele - com bus" receive input data bus. all incoming sts-12/stm-4 data is sampled and latched (into the xrt94l43 via these input pins) upon the rising edge of the rxd_clk" input pin. n otes : 1. 1.the user must insure that the msb (most significant bit) of each incoming byte is input to the rxd_d7 input pin. 2. the user must also insure that the lsb (least significant bit) of each incoming byte is input to the rxd_d0 input pin. 3. the user should tie these pins to gnd if the sts-12/stm-4 telecom bus is not enabled. sts-12/stm-4 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 24 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper sonet/sdh overhead interf ace - transmit direction p in # s ignal n ame i/o s ignal t ype d escription h2 txtohclk o cmos transmit toh input port - clock output: this output pin, along with the tx tohenable, txtohframe output pins and the txtoh and txtohins input pins function as the transmit toh input port. the transmit toh input port allows t he user to insert their own value for the toh bytes (in the outbound sts-12/stm-4 signal). this output pin provides a clock sign al. if the txtohenable output pin is "high" and if the txtohins input pin is pulled "high", then the user is expected to provide a given bit (withi n the toh) to the txtoh input pin, upon the falling edge of this clock signal. the data, residing on the txtoh input pin will be latched into the xrt94l43 upon the rising edge of this clock signal. n ote : the transmit toh input port only support the insertion of the toh within the first sts-1, wit hin the outbound sts-12 signal. h4 txtohenable o cmos transmit toh input port - toh enable (or ready) indicator: this output pin, along with the tx tohclk, txtohframe output pins and the txtoh and txtohins input pins function as the transmit toh input port. this output pin will toggle and remain "high" anytime the transmit toh input port is ready to externally accept toh data. if it is desired to externally insert a value of toh into the outbound sts- 12 data stream via the transmit toh input port, then do the following: ? continuously sample the state of txtohframe and this output pin upon the rising edge of txtohclk. ? whenever this output pin pulses "high", then the user's external circuitry should drive the txtohins input pin "high". ? next, the user should output the next toh bit, onto the txtoh input pin, upon the falling edge of txtohclk. d1 txtoh i ttl transmit toh input port - input pin: this input pin, along with the tx tohins input pin, the txtohenable and txtohframe and txtohclk output pins function as the transmit toh input port. if it is desired to externally insert a value of toh into the outbound sts- 12 data stream via the transmit toh input port, then do the following: ? continuously sample the state of txtohframe and txtohenable upon the rising edge of txtohclk. ? whenever txtohenable pulses " high", then the user's external circuitry should drive the txtohins input pin "high". ? next, the user should output the next toh bit, onto this input pin, upon the falling edge of txtohclk. the transmit toh input port will sample the data (on this input pin) upon the rising edge of txtohclk. n ote : data at this input pin will be ignored (e.g., not sampled) unless the txtohenable output pin is "high" and the txtohins input pin is pulled "high".
xrt94l43 25 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 g4 txtohframe o cmos transmit toh input port - sts-12/stm-4 frame indicator: this output pin, along with txto hclk, txtohenable output pins, and the txtoh and txtohins input pins function as the transmit toh input port. this output pin will pulse "high" (f or one period of txtohclk), one txtohclk clock period prior to the first toh bit of a given sts-12 frame, being expected vi a the txtoh input pin. if it is desired to externally insert a value of toh into the outbound sts- 12 data stream via the transmit toh input port, then do the following: ? continuously sample the state of txtohenable and this output pin upon the rising edge of txtohclk. ? whenever the txtohenable output pi n pulse "high", then the user's external circuitry should drive the txtohins input pin "high". ? next, the user should output the next toh bit, onto the txtoh input pin, upon the falling edge of txtohclk. n ote : the external circuitry (which is being interfaced to the transmit toh input port can use this output pin to denote the boundary of sts-12 frames. c1 txtohins i ttl transmit toh input port - insert enable input pin: this input pin, along with the tx toh input pin, and the txtohenable, txtohframe and txtohclk output pins function as the transmit toh input port. this input pin is used to either enable or disable the transmit toh input port. if this input pin is "low", then the transmit toh input port will be dis - abled and will not sample and insert (into the outbound sts-12 data stream) any data residing on the txtoh input, upon the rising edge of txtohclk. if this input pin is "high", then the transmit toh input port will be enabled. in this mode, whenever th e txtohenable output pin is also "high", the transmit toh input port will sample and latch any data that is presented on the txtoh input pin, upon the rising edge of txtohclk. if it is desired to externally insert a value of toh into the outbound sts- 12 data stream via the transmit toh input port, then do the following: ? continuously sample the state of txtohframe and txtohenable upon the rising edge of txtohclk. ? whenever the txtohenable output pin is sampled "high" then the user's external circuitry should drive this input pin "high". ? next, the user should output the next toh bit, onto the txtoh input pin, upon the falling edge of txto hclk. the transmit toh input port will sample the data (on this input pin) upon the rising edge of txtohclk. n ote : data applied to the txtoh input pin will be ignored (e.g., not sampled) unless then the txtohenable and this input pin are each "high". sonet/sdh overhead interf ace - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 26 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper g3 txldccenable o cmos transmit - line dcc input port - enable output pin: this output pin, along with the txtohclk output pin and the txldcc input pin are used to insert the value for the d4, d5, d6, d7, d8, d9, d10, d11 and d12 bytes into the transmit sts-12 toh processor block. the transmit sts-12 toh processor block will accept this data and will insert into the d4, d5, d6, d7, d8, d9, d10, d11 and d12 byte- fields, within the outbound sts-12 data-stream. the line dcc hdlc controller circuitr y (which is connected to the txtohclk, the txldcc and this output pin, is suppose to do the follow - ing. 1. it should continuously monito r the state of this output pin. 2. whenever this output pin pulses "high", then the line dcc hdlc controller circuitry should place the next line dcc bit (to be inserted into the transmit sts-12 toh processor block) onto the txldcc input pin, upon the falling edge of txtohclk. 3. any data that is placed on the txldcc input pin, will be sampled upon the rising edge of txohclk. j4 txsdccenable o cmos transmit - section dcc input port - enable output pin: this output pin, along with the tx tohclk output pin and the txsdcc input pin are used to insert the value for the d1, d2 and d3 bytes, into the transmit sts-12 toh processor block. the transmit sts-12 toh processor block will accept this data and will insert into the d1, d2 and d3 byte-fields, within th e outbound sts-12 data-stream. the section dcc hdlc controller circuitry (which is connected to the txtohclk, the txsdcc and this output pin, is suppose to do the follow - ing. 1. it should continuously monito r the state of this output pin. 2. whenever this output pin pulses "high", then the section dcc hdlc controller circuitry should place the next section dcc bit (to be inserted into the transmit sts-12 toh processor block) onto the txsdcc input pin, upon the falling edge of txtohclk. 3. any data that is placed on the txsdcc input pin, will be sampled upon the rising edge of txohclk. e2 txsdcc i ttl transmit - section dcc input port - input pin: this input pin, along with the txsdccenable and the txtohclk output pins are used to insert a value for the d1, d2 and d3 bytes, into the transmit sts-12 toh processor block. the transmit sts-12 toh processor block will accept this data and insert it into the d1, d2 and d3 byte fields, within the outbound sts-12 data-stream. the section dcc hdlc circuitry that is interfaced to this input pin, the txsdccenable and the txtohclk pins is suppose to do the following. 1. it should continuously monitor the state of the txsdccenable input pin. 2. whenever the txsdccenable input pin pulses "high", then the sec - tion dcc hdlc controller circuitry should place the next section dcc bit (to be inserted into the transmit sts-12 toh processor block) onto this input pin upon the falling edge of txtohclk. 3. any data that is placed on the txsdcc input pin, will be sampled upon the rising edge of txtohclk. n ote : tie this pin to gnd if it is not going to be used. sonet/sdh overhead interf ace - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 27 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 h3 txldcc i ttl transmit - line dcc input port: this input pin, along with the txldccenable and the txtohclk pins are used to insert a value for the d4, d5, d6, d7, d8, d9, d10, d11 and d12 bytes, into the transmit sts-12 toh processor block. the trans - mit sts-12 toh processor block will accept this data and insert it into the d4, d5, d6, d7, d8, d9, d10, d1 1 and d12 byte-fields, within the outbound sts-12 data-stream. whatever line dcc hdlc controller circu itry is interface to the this input pin, the txldccenable and t he txtohclk is suppose to do the following. 1. it should continuously monitor t he state of the txldccenable input pin. 2. whenever the txldccenable input pin pulses "high", then the sec - tion dcc interface circuitry should place the next line dcc bit (to be inserted into the transmit sts-12 toh processor block) onto the txldcc input pin, upon the falling edge of txtohclk. 3. any data that is placed on the txldcc input pin, will be sampled upon the rising edge of txtohclk. n ote : tie this pin to gnd, if it is not going to be used. f4 txe1f1e2enable o cmos transmit e1-f1-e2 byte input port - enable (or ready) indicator output pin: this output pin, along with the tx tohclk output pin and the txe1f1e2 input pin are used to insert a value fo r the e1, f1 and e2 bytes, into the transmit sts-12 toh processor block. the transmit sts-12 toh processor block will accept this data and will insert into the e1, f1 and e2 byte-fields, within the outbound sts-12 data-stream. whatever external circuitry (which is connected to the txtohclk, the txe1f1e2 and this output pin, is suppose to do the following. 1. it should continuously monito r the state of this output pin. 2. whenever this output pin pulses "high", then the external circuitry should place the next orderwire bit (to be inserted into the transmit sts-12 toh processor block) onto the txe1f1e2 input pin, upon the falling edge of txtohclk. any data that is placed on the txe1f1e2 input pin, will be sampled upon the rising edge of txohclk. d2 txe1f2e2frame o cmos transmit e1-f1-e2 byte inpu t port - framin g output pin: this output pin pulses "high" for one period of txtohclk, one txto - hclk bit-period prior to the transmit e1-f1-e2 byte input port expecting the very first byte of the e1 byte , within a given outbound sts-12 frame. sonet/sdh overhead interf ace - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 28 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper j6 txe1f1e2 i ttl transmit e1-f1-e2 byte input port - input pin: this input pin, along with the txe1f1e2enable and the txtohclk out - put pins are used to insert a value for the e1, f1 and e2 bytes, into the transmit sts-12 toh processor block. the transmit sts-12 toh processor block will accept this data and insert it into the e1, f1 and e2 byte fields, within the outbound sts-12 data-stream. whatever external circuitry that is interfaced to this input pin, the txe1f1e2enable and the txtohclk pins is suppose to do the follow - ing. 1. it should continuously monitor the state of the txe1f1e2enable input pin. 2. whenever the txe1f1e2enable input pin pulses "high", then the external circuitry should place the next orderwire bit (to be inserted into the transmit sts-12 toh processor bl ock) onto this input pin upon the falling edge of txtohclk. 3. any data that is placed on the txe1f1e2 input pin, will be sampled upon the rising edge of txtohclk. n ote : tie this pin to gnd if it is not going to be used. sonet/sdh overhead interf ace - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 29 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 c10 b13 ad12 ad8 a16 d18 ad13 ae8 d13 c18 ae17 ab12 d9 c13 ae11 af4 txpoh_0 txpoh_1 txpoh_2 txpoh_3 txpoh_4 txpoh_5 txpoh_6 txpoh_7 txpoh_8 txpoh_9 txpoh_10 txpoh_11 txpoh_12 txpoh_13 txpoh_14 txpoh_15 i ttl transmit path overhead input port - input pin. these input pins allow the following actions. 1. insertion oft the poh data into each of the 12 transmit sonet poh processor blocks (for insertion and transmission via the outbound sts- 12 signal. 2. insertion of the poh data into each of the 12 transmit sts-1 poh processor blocks (for insertion and transmission via each of the out - bound sts-1 signals). 3. insertion of the toh data into each of the 12 transmit sts-1 toh processor blocks (for insertion and transmission via each of the out - bound sts-1 signals). the function of these input pins, depends upon whether or not the toh data is inserted into the 12 tr ansmit sts-1 toh processor blocks. if the user is only inserting poh data via these input pins: in this mode, the external circuitr y (which is being interfaced to the transmit path overhead input port is suppose to monitor the following output pins. ? txpohframe_n ? txpohenable_n ? txpohclk_n the txpohframe_n output pin will toggle "high" upon the falling edge of txpohclk_n approximately one txpohclk_n period prior to the txpoh port being ready to accept and process the first bit within the j1 byte (e.g., the first poh byte). the txpohframe_n output pin will remain "high" for eight consecutiv e txpohclk_n periods. the external circuitry should use this pin to note sts- 1 spe frame boundaries. the txpohenable_n output pin will toggle "high" upon the falling edge of txpohclk_n approximately one txpohclk_n period prior to the txpoh port being ready to accept and process the first bit within a given poh byte. to externally insert a given poh by te, (1) assert the txpohins_n input pin by toggling it "high" and (2) place the value of the first bit (within this particular poh byte) on this input pin upon the very next falling edge of txpohclk_n. this data bit will be sampled upon the very next rising edge of txpohclk_n. the external circ uitry should continue to keep the txpohins_n input pin "high" and adv ancing the next bits (within the poh bytes) upon each falling edge of txpohclk_n. if the user is inserting both poh and toh data via these input pins: in this mode, the external circuitr y (which is being interfaced to the transmit path overhead input port is suppose to monitor the following output pins. ? txpohframe_n ? txpohenable_n ? txpohclk_n (continued below) sonet/sdh overhead interf ace - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 30 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper c10 b13 ad12 ad8 a16 d18 ad13 ae8 d13 c18 ae17 ab12 d9 c13 ae11 af4 txpoh_0 txpoh_1 txpoh_2 txpoh_3 txpoh_4 txpoh_5 txpoh_6 txpoh_7 txpoh_8 txpoh_9 txpoh_10 txpoh_11 txpoh_12 txpoh_13 txpoh_14 txpoh_15 i ttl if the user is inserting both poh and toh data via these input pins: (continued) the txpohframe_n output pin will togg le "high" twice during a given sts-1 frame period. first, this outpu t pin will toggle "high" coincident with the txpoh port being ready to accept and process the a1 byte (e.g., the very first toh byte). second, this output pin will toggle "high" coincident with the txpoh port being ready to accept and process the j1 byte (e.g., the very first poh byte). if the externally circuitry samples the txpohframe_n output pin "high", and the txpohenable_n output pin " low", then the txpoh port is now ready to accept and process the very first toh byte. if the externally circuitry samples the txpohframe_n output pin "high" and the txpohenable_n output pin " high", then the txpoh port is now ready to accept and process the very first poh byte. to externally insert a given poh or toh byte, do the following; (1) assert the txpohins_n input pin by toggling it "high" and, (2) place the value of the first bit (within this particular poh or toh byte) on this input upon the very next falling edge of txpohclk_n. this data bit will be sampled upon the very next rising edge of txpohclk_n. the external circuitry should continue to keep the txpohins_n input pin "high" and adv ancing the next bits (within the poh bytes) upon each falling edge of txpohclk_n. n otes : 1. if poh data is externally inserted into each of the 12 transmit sonet poh processor blocks, th en these input pins cannot be used to externally insert poh data into each of the 12 transmit sts-1 poh processor blocks. 2. toh data can be externally inserted into each of the 12 transmit sts-1 toh processor blocks, only if poh data is not externally inserted into each of the 12 transmit sonet poh processor blocks. b10 a15 ac13 ad9 b16 d19 ae13 ae9 d14 c19 af19 ab13 e10 c14 af11 af5 txpohclk_0 txpohclk_1 txpohclk_2 txpohclk_3 txpohclk_4 txpohclk_5 txpohclk_6 txpohclk_7 txpohclk_8 txpohclk_9 txpohclk_10 txpohclk_11 txpohclk_12 txpohclk_13 txpohclk_14 txpohclk_15 o cmos transmit path overhead input port - clock output pin: these output pins, along with txpoh_n, txpohenable_n, txpohins_n and txpohframe_n func tion as the transmit path over - head (txpoh) input port. the txpohframe_n and txpohenable_n output pins are updated upon the falling edge this clock output signal. the txpohins_n input pins and the data residing on the txpoh_n input pins are sampled on the rising edge of this clock signal. sonet/sdh overhead interf ace - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 31 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 a6 a11 ac12 ad7 d8 b12 af14 ab10 a12 c17 aa15 ac10 d7 e11 ac11 ad6 txpohframe_0 txpohframe_1 txpohframe_2 txpohframe_3 txpohframe_4 txpohframe_5 txpohframe_6 txpohframe_7 txpohframe_8 txpohframe_9 txpohframe_10 txpohframe_11 txpohframe_12 txpohframe_13 txpohframe_14 txpohframe_15 o cmos transmit path overhead input port - frame output pin: these output pins, along with the txpoh_n, txpohenable_n, txpohins_n and txpohclk_n function as the transmit path overhead input port. the function of these output pins depends upon whether poh or toh data is inserted via the txpoh_n input pins. if the user is only inserting poh data via these input pins: in this mode, the txpoh port will pu lse these output pins "high" when - ever it is ready to accept and proces s the j1 byte (e.g., the very first poh byte) via this port. if the user is inserting both poh and toh data via these input pins: in this mode, the txpoh port will pu lse these output pins "high" coinci - dent with the following. 1. whenever the txpoh port is ready to accept and process the a1 byte (e.g., the very first toh byte) via this port. 2. whenever the txpoh port is ready to accept and process the j1 byte (e.g., the very first poh byte) via this port. n ote : the external circuitry can dete rmine whether the txpoh port is expecting the a1 byte or the j1 byte, by checking the state of the corresponding txpohenable output pin. if the txpohenable_n output pin is "low" while the txpohframe_n output pin is "high", then the txpoh port is ready to process the a1 (toh) bytes. if the txpohenable_n output pin is "high" while the txpohframe_n output pin is "high", then the txpoh port is ready to process the j1 (poh) bytes. sonet/sdh overhead interf ace - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 32 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper a7 c12 ae12 ac9 e9 a13 af16 ab11 e13 d17 ac16 af8 e8 e12 af9 ac8 txpohins_0 txpohins_1 txpohins_2 txpohins_3 txpohins_4 txpohins_5 txpohins_6 txpohins_7 txpohins_8 txpohins_9 txpohins_10 txpohins_11 txpohins_12 txpohins_13 txpohins_14 txpohins_15 i ttl transmit path overhead input port - insert enable input pin: these input pins, along wit h txpoh_n, txpohenable_n, txpohframe_n and txpohclk_n function as the transmit path over - head (txpoh) input port. these input pins are used to enable or disable the txpoh input port. if these input pins are pulled "high" , then the txpoh port will sample and latch data via the corresponding txpoh input pins, upon the rising edge of txpohclk_n. conversely, if these input pins ar e pulled "low", then the txpoh port will not sample and latch data via the corresponding txpoh input pins. n ote : if the txpohins_n input pin is pu lled "low", this setting will be overridden if, the transmit sonet/sts-1 poh processor or transmit sts-1 toh processor blo cks are configured to accept certain poh or toh overhead bytes via the external port. d10 d15 ab14 ae7 a10 a17 ac14 af7 c11 b14 ad14 ae10 b11 d16 af13 ab9 txpohenable_0 txpohenable_1 txpohenable_2 txpohenable_3 txpohenable_4 txpohenable_5 txpohenable_6 txpohenable_7 txpohenable_8 txpohenable_9 txpohenable_10 txpohenable_11 txpohenable_12 txpohenable_13 txpohenable_14 txpohenable_15 o cmos transmit path overhead input port - poh indicator output pin: these output pins, along with txpoh_ n, txpohins_n, txpohframe_n and txpohclk_n function as the transmit path overhead (txpoh) input port. these output pins will pulse "high" anytime the txpoh port is ready to accept and process poh bytes. th ese output pins will be "low" at all other times. sonet/sdh overhead interf ace - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 33 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 sts-3/stm-1 telecom bus interface - transmit direction p in # s ignal n ame i/o s ignal t ype d escription e15 sts3txa_clk_0 txsbclk_0 dmo_0 i ttl sts-3 transmit telecom bus clock input/stm-1 sub-rate clock/dmo_0 (general purpose) input pin: the function of this input pin depen ds upon whether or not thests-3/ stm-1 telecom bus interface for channel 0 has been enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3 transmit telecom bus transmit clock input - channel 0: this input clock signal functions as the clock source for the sts-3/ stm-1 transmit telecom bus, associated with channel 0. all input signals (e.g., sts3txa_alarm_0, sts3txa_d_0[7:0], sts3txa_dp_0, sts3txa_pl_0, sts3txa_c1j1_0) are sampled upon the falling edge of this input clock signal. this clock signal should operate at 19.44mhz. if sts-3/stm-1 telecom bus (cha nnel 0) is disabled - dmo_0 (general purpose) input pin: this input pin can be used as a general purpose input pin. the state of this input pin can be determined by reading the state of bit 2 (dmo) within the line interface scan register associated with channel 0 (address = 0x1e, 0x81), (direct address = 0x1f81). n ote : for product legacy purposes, this pin is called dmo_0, because one possible application is to tie this input pin to a dmo (drive monitor output) outp ut pin, from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this input pin, and the corresponding register bit can be used for any purpose. c26 sts3txa_clk_1 txsbclk_1 dmo_1 i ttl sts-3 transmit telecom bus clock input/stm-1 sub-rate clock/dmo_1 (general purpose) input pin: see definition of pin # e15 above replacing channel 0 with channel 1. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3 transmit telecom bus clock input - channel 1: if sts-3/stm-1 telecom bus (cha nnel 1) is disabled - dmo_1 (general purpose) input pin: ae25 sts3txa_clk_2 txsbclk_2 dmo_2 i ttl sts-3 transmit telecom bus clock input/stm-1 sub-rate clock/dmo_2 (general purpose) input pin: see definition of pin # e15 above replacing channel 0 with channel 2. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3 transmit telecom bus transmit clock input - channel 2: if sts-3/stm-1 telecom bus (cha nnel 2) is disabled - dmo_2 - drive monitor output input (from xrt73l0x liu ic) - channel 2:
xrt94l43 34 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ad17 sts3txa_clk_3 txsbclk_3 dmo_3 i ttl sts-3 transmit telecom bus clock input/stm-1 sub-rate clock/dmo_3 (general purpose) input pin: see definition of pin # e15 above replacing channel 0 with channel 3. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3 transmit telecom bus clock input - channel 3: if sts-3/stm-1 telecom bus (cha nnel 3) is disabled - dmo_3 (general purpose) input pin: e14 sts3txa_pl_0 txsbframe_0 rlol_0 i ttl transmit sts-3/stm-1 telecom bus interface - payload indica - tor signal - channel 0/rlol_0 (general purpose) input pin: the function of this input depends upon whether or not thests-3/ stm-1 telecom bus interface for channel 0 has been enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - transmit sts-3/stm-1 telecom bus interface - payload indica - tor signal - channel 0: this input pin indicates whether or not transport overhead (toh) bytes are being input via th e txa_d_0[7:0] input pins. this input pin should be pulled "low" for the duration that the sts-3/ stm-1 transmit telecom bus is receiving a toh byte, via the txa_d_0[7:0] input pins. n ote : this input signal is sampled upon the falling edge of sts3txa_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - rlol_0 (general purpose) input pin. this input pin can be used as a general purpose input pin. the state of this input pin can be determined by reading the state of bit 1 (rlol) within the line interface scan register associated with channel 0 (address = 0x1e, 0x81), (direct address = 0x1f81). n ote : for product legacy purposes, this pin is called rlol_0 because one possible application is to tie this input pin to a rlol (receive loss of lock) out put pin, from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this input pin and the corresponding register bit can be used for any purpose. a26 sts3txa_pl_1 txsbframe_1 rlol_1 i ttl transmit sts-3/stm-1 telecom bus interface - payload indica - tor signal - channel 1/rlol_1 (general purpose) input pin: see definition of pin # e14 above replacing channel 0 with channel 1. if sts-3/stm-1 telecom bus (channel 1) has been enabled - transmit sts-3/stm-1 telecom bus interface - payload indica - tor signal - channel 1: if sts-3/stm-1 telecom bus (channel 1) is disabled - rlol_1 (general purpose) input pin: sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 35 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ad25 sts3txa_pl_2 txsbframe_2 rlol_2 i ttl transmit sts-3/stm-1 telecom bus interface - payload indica - tor signal - channel 2/rlol_2 (general purpose) input pin: see definition of pin # e15 above replacing channel 0 with channel 2. if sts-3/stm-1 telecom bus (channel 2) has been enabled - transmit sts-3/stm-1 telecom bus interface - payload indica - tor signal - channel 2: if sts-3/stm-1 telecom bus (channel 2) is disabled - rlol_2 (general purpose) input pin: ab17 sts3txa_pl_3 txsbframe_3 rlol_3 i ttl transmit sts-3/stm-1 telecom bus interface - payload indica - tor signal - channel 3/rlol_3 (general purpose) input pin: see definition of pin # e15 above replacing channel 0 with channel 3. if sts-3/stm-1 telecom bus (channel 3) has been enabled - transmit sts-3/stm-1 telecom bus interface - payload indica - tor signal - channel 3: if sts-3/stm-1 telecom bus (channel 3) is disabled - rlol_3 (general purpose) input pin: sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 36 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper b24 sts3txa_c1j1_0 ing_lcv_in_8 ing_rxneg_in_8 txsts1pl_8 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus interface c1/j1 byte phase indicator input signal (channel 0); ds3/e3 framer block lcv/ rxneg input pin - channel 8: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface for trlrcom bus channel 0 has been enabled. if sts-3/stm-1 telecom bus (tel ecom bus channel 0) has been enabled - transmit sts-3/stm-1 telecom bus interface c1/j1 byte phase indicator input signal (channel 0): this input pin should be pulsed "high" during both of the following conditions. 1. whenever the c1 byte is being input to the sts-3/stm-1 transmit telecom bus (txa_d_0[7:0]) input pins. 2. whenever the j1 byte is being input to the sts-3/stm-1 transmit telecom bus (txa_d_0[7:0]) input pins. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3 framer block lcv/neg input - channel 8: if the sts-3/stm-1 telecom bus (channel 0) is disabled and if the ds3/e3 framer block (associated with channel 8) is enabled then this pin will function as either an lcv or an rxneg input pin. if channel 8 is configured to operate in the single- rail mode, and if the primary frame synchronizer block is configured to operate in the ingress path - ing_lcv_in_8 input pin: if the primary frame synchronizer block (associated with channel 8) is configured to operate in the ingress path, and if channel 8 is con - figured to operate in the single-rail mode, then this input pin will function as the "lcv" (line code violation) input pin. in this case, the user should connect this particular input pin to the "lcv" output pin of the corresponding ds3/e3/sts-1 liu channel. if channel 8 is configured to operate in the dual-rail mode, and if the primary frame synchronizer block is configured to oper - ate in the ingress path - ing_rxneg_in_8: if the primary frame synchronizer bl ock (associated with channel 8) is configured to operate in the ingress path, and if channel 8 is con - figured to operate in the dual-rail mode, then this input pin will func - tion as the "rxneg" (negative polarity data) input pin. in this case, the user should connect this particular input to the "rxneg" output pin of the corresponding ds3/e3/sts-1 liu channel. n ote : this pin is inactive if the pr imary frame synchronizer block (associated with channel 8) is not configured to operate in the ingress path. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 37 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 j23 sts3txa_c1j1_1 ing_lcv_in_9 ing_rxneg_in_9 txsbframe_1 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus interface - c1/j1 byte phase indicator input signal (cha nnel 1); ds3/e3 framer block lcv/rxneg input pin - channel 9: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface for telecom bus channel 1 has been enabled. if sts-3/stm-1 telecom bus (tel ecom bus channel 1) has been enabled - transmit sts-3/stm-1 telecom bus interface c1/j1 byte phase indicator input signal (channel 1): this input pin should be pulsed "high" during both of the following conditions. 1. whenever the c1 byte is being input to the sts-3/stm-1 transmit telecom bus (txa_d_1[7:0]) input pins. 2. whenever the j1 byte is being input to the sts-3/stm-1 transmit telecom bus (txa_d_1[7:0]) input pins. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3 framer block lcv/rxneg input - channel 9): if the sts-3/stm-1 telecom bus (channel 1) is disabled and if the ds3/e3 framer block is enabled then this pin will function as either an lcv or rxneg input pin. if channel 9 is configured to operate in the single- rail mode, and if the primary frame synchronizer block is configured to operate in the ingress path - ing_lcv_in_9 input pin: if the primary frame synchronizer block (associated with channel 9) is configured to operate in the ingress path, and if channel 8 is con - figured to operate in the single-rail mode, then this input pin will function as the "lcv" (line code violation) input pin. in this case, the user should connect this particular input pin to the "lcv" output pin of the corresponding ds3/e3/sts-1 liu channel. if channel 9 is configured to operate in the dual-rail mode, and if the primary frame synchronizer block is configured to oper - ate in the ingress path - ing_rxneg_in_9: if the primary frame synchronizer bl ock (associated with channel 9) is configured to operate in the ingress path, and if channel 9 is con - figured to operate in the dual-rail mode, then this input pin will func - tion as the "rxneg" (negative polarity data) input pin. in this case, the user should connect this particular input to the "rxneg" output pin of the corresponding ds3/e3/sts-1 liu channel. n ote : this pin is inactive if the pr imary frame synchronizer block (associated with channel 9) is not configured to operate in the ingress path. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 38 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper af24 sts3txa_c1j1_2 ing_lcv_in_10 ing_rxneg_in_10 txsts1pl_10 txsbframe_2 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus interface - c1/j1 byte phase indicator input signal (cha nnel 2); ds3/e3 framer block lcv/rxneg input pin - channel 10: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface for channel 2 has been enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus c1/j1 byte phase indicator input signal (channel 2): this input pin should be pulsed "high" during both of the following conditions. 1. whenever the c1 byte is being input to the sts-3/stm-1 transmit telecom bus (txa_d_2[7:0]) input pins. 2. whenever the j1 byte is being input to the sts-3/stm-1 transmit telecom bus (txa_d_2[7:0]) input pins. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3 framer block lcv/rxneg input - channel 10): if the sts-3/stm-1 telecom bus (channel 2) is disabled and if the ds3/e3 framer block is enabled then this pin will function as either an lcv or an rxneg input pin. if channel 10 is configured to operate in the single- rail mode, and if the primary frame synchronizer block is configured to operate in the ingress path - ing_lcv_in_10 input pin: if the primary frame synchronizer block (associated with channel 10) is configured to operate in t he ingress path, and if channel 10 is configured to operate in the single -rail mode, then this input pin will function as the "lcv" (line code violation) input pin. in this case, the user should connect this particular input pin to the "lcv" output pin of the corresponding ds3/e3/sts-1 liu channel. if channel 10 is configured to operate in the dual-rail mode, and if the primary frame synchronizer block is configured to operate in the ingress path - ing_rxneg_in_10: if the primary frame synchronizer block (associated with channel 10) is configured to operate in t he ingress path, and if channel 10 is configured to operate in the dual-rail mode, then this input pin will function as the "rxneg" (negative polarity data) input pin. in this case, the user should connect this particular input to the "rxneg" output pin of the correspondin g ds3/e3/sts-1 liu channel. n ote : this pin is inactive if the pr imary frame synchronizer block (associated with channel 10) is not configured to operate in the ingress path. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 39 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 af17 sts3txa_c1j1_3 ing_lcv_in_11 ing_rxneg_in_11 txsts1pl_11 txsbframe_3 i/o ttl/ cmos sts-3/stm-1 transmit telecom bus c1/j1 byte phase indicator input signal (channel 3); ds3/e3 frame generator framing pulse input/output pin - channel 11: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface for telecom bus channel 3 has been enabled. if sts-3/stm-1 telecom bus (tel ecom bus channel 3) has been enabled - sts-3/stm-1 transmit telecom bus c1/j1 byte phase indicator input signal (channel 3): this input pin should be pulsed "high" during both of the following conditions. 1. whenever the c1 byte is being input to the sts-3/stm-1 transmit telecom bus (txa_d_3[7:0]) input pins. 2. whenever the j1 byte is being input to the sts-3/stm-1 transmit telecom bus (txa_d_3[7:0]) input pins. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3 framer block lcv/rxneg input - channel 11) :if the sts-3/stm-1 telecom bus (channel 3) is disabled and if the ds3/e3 framer block (associated with channel 11) is enabled then this pin will function as either an lcv or an rxneg input pin. if channel 11 is configured to operate in the single- rail mode, and if the primary frame synchronizer block is configured to operate in the ingress path - ing_lcv_in_11 input pin: if the primary frame synchronizer block (associated with channel 11) is configured to operate in the ingress path, and if channel 11 is configured to operate in the single- rail mode, then this input pin will function as the "lcv" (line code violation) input pin. in this case, the user should connect this particular input pin to the "lcv" output pin of the corresponding ds3/e3/sts-1 liu channel. if channel 11 is configured to operate in the dual-rail mode, and if the primary frame synchronizer block is configured to oper - ate in the ingress path - ing_rxneg_in_11: if the primary frame synchronizer block (associated with channel 11) is configured to operate in the ingress path, and if channel 8 is configured to operate in the dual-rail mode, then this input pin will function as the "rxneg" (negative polarity data) input pin. in this case, the user should connect this particular input to the "rxneg" output pin of the correspondin g ds3/e3/sts-1 liu channel. n ote : this pin is inactive if the pr imary frame synchronizer block (associated with channel 11) is not configured to operate in the ingress path. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 40 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper b22 sts3txa_dp_0 ing_lcv_in_4 ing_rxneg_in_4 txsts1pl_4 i/o ttl/ cmos transmit sts-3/stm-1 telecom bu s - parity inpu t pin - channel 0; ds3/e3 framer blocklcv/rxneg input pin - channel 4: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface for telecom bus channel 0 has been enabled. if sts-3/stm-1 telecom bus telecom bus (channel 0) has been enabled -transmit sts-3/stm-1 telecom bus interface - parity input pin: this input pin can be configured to function as one of the following. 1. the even or odd parity value of the bits which are input via the st3txa_d_0[7:0] input pins. 2. the even or odd parity value of the bits which are being input via the sts3txa_d_0[7:0] input and the states of the sts3txa_pl_0 and sts3txa_c1j1_0 input pins. n ote : any one of these configurati on selections can be made by writing the appropriate value into the interface control register - byte 0 register (i ndirect address = 0x00, 0x3b), (direct address = 0x013b). if sts-3/stm-1 telecom bus (telecom bus channel 0) is dis - abled - ds3/e3 framer block lcv/rxneg input - channel 4): if the sts-3/stm-1 telecom bus (channel 0) is disabled and if the ds3/e3 framer block (associated with channel 4) is enabled then this pin will function as either an lcv or an rxneg input pin. if channel 4 is configured to operate in the single- rail mode, and if the primary frame synchronizer block is configured to operate in the ingress path - ing_lcv_in_4 input pin: if the primary frame synchronizer block (associated with channel 4) is configured to operate in the ingress path, and if channel 4 is con - figured to operate in the single-rail mode, then this input pin will function as the "lcv" (line code violation) input pin. in this case, the user should connect this particular input pin to the "lcv" output pin of the corresponding ds3/e3/sts-1 liu channel. if channel 8 is configured to operate in the dual-rail mode, and if the primary frame synchronizer block is configured to oper - ate in the ingress path - ing_rxneg_in_4: if the primary frame synchronizer bl ock (associated with channel 4) is configured to operate in the ingress path, and if channel 4 is con - figured to operate in the dual-rail mode, then this input pin will func - tion as the "rxneg" (negative polarity data) input pin. in this case, the user should connect this particular input to the "rxneg" output pin of the corresponding ds3/e3/sts-1 liu channel. n ote : this pin is inactive if the pr imary frame synchronizer block (associated with channel 4) is not configured to operate in the ingress path. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 41 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 g23 sts3txa_dp_1 ing_lcv_in_5 ing_rxneg_in_5 txsts1pl_5 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus interface - parity input pin - channel 1, ds3/e3 framer bl ock lcv/rxneg input pin - chan - nel 5: the function of this input pin depends upon whether or not the sts- 3/stm-1 telecom bus interface for channel 1 has been enabled. if sts-3/stm-1 telecom bus (transmit channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - parity input pin: this input pin can be configured to function as one of the following. 1. the even or odd parity value of the bits which are input via the st3txa_d_1[7:0] input pins. 2. the even or odd parity value of the bits which are being input via the sts3txa_d_1[7:0] input and the states of the sts3txa_pl_1 and sts3txa_c1j1_1 input pins. n ote : any one of these configurati on selections can be made by writing the appropriate value into the interface control register - byte 1 register (i ndirect address = 0x00, 0x3a), (direct address = 0x013a). if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3 framer block lcv/rxneg input - channel 5: if the sts-3/stm-1 telecom bus (channel 1) is disabled and if the ds3/e3 framer block (associated with channel 5) is enabled then this pin will function as either an lcv or an rxneg input pin. if channel 5 is configured to operate in the single- rail mode, and if the primary frame synchronizer block is configured to operate in the ingress path - ing_lcv_in_5 input pin: if the primary frame synchronizer block (associated with channel 5) is configured to operate in the ingress path, and if channel 5 is con - figured to operate in the single-rail mode, then this input pin will function as the "lcv" (line code violation) input pin. in this case, the user should connect this particular input pin to the "lcv" output pin of the corresponding ds3/e3/sts-1 liu channel. if channel 5 is configured to operate in the dual-rail mode, and if the primary frame synchronizer block is configured to oper - ate in the ingress path - ing_rxneg_in_5: if the primary frame synchronizer bl ock (associated with channel 5) is configured to operate in the ingress path, and if channel 5 is con - figured to operate in the dual-rail mode, then this input pin will func - tion as the "rxneg" (negative polarity data) input pin. in this case, the user should connect this particular input to the "rxneg" output pin of the corresponding ds3/e3/sts-1 liu channel. n ote : this pin is inactive if the pr imary frame synchronizer block (associated with channel 5) is not configured to operate in the ingress path. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 42 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ae24 sts3txa_dp_2 ing_lcv_in_6 ing_rxneg_in_6 txsts1pl_6 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus interface - parity input pin - channel 2, ds3/e3 framer blo ck lcv/rxneg input pin - channel 6: the function of this input pin depends upon whether or not the sts-3/ stm-1 telecom bus interface for channel 2 has been enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - transmit sts-3/stm-1 telecom bus interface - parity input pin: this input pin can be configured to function as one of the following. 1. the even or odd parity value of the bits which are input via the st3txa_d_2[7:0] input pins. 2. the even or odd parity value of the bits which are being input via the sts3txa_d_2[7:0] input and the states of the sts3txa_pl_2 and sts3txa_c1j1_2 input pins. n ote : any one of these configurati on selections can be made by writing the appropriate value into the interface control register - byte 2 register (indirect address = 0x00, 0x39), (direct address = 0x0139). if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3 framer block lcv/rxneg input - channel 6): if the sts-3/stm-1 telecom bus (channel 2) is disabled and if the ds3/e3 framer block (associated with channel 6) is enabled then this pin will function as either an lcv or an rxneg input pin. if channel 6 is configured to operate in the single-rail mode, and if the primary frame synchronizer block is configured to operate in the ingress path - ing_lcv_in_6 input pin: if the primary frame synchronizer block (associated with channel 6) is configured to operate in the ingress path, and if channel 6 is con - figured to operate in the single-rail mode, then this input pin will func - tion as the "lcv" (line code violation" input pin. in this case, the user should connect this particular input pin to the "lcv" output pin of the corresponding ds3/e3/sts-1 liu channel. if channel 6 is configured to operate in the dual-rail mode, and if the primary frame synchronizer block is configured to operate in the ingress path - ing_rxneg_in_6: if the primary frame synchronizer bl ock (associated with channel 6) is configured to operate in the ingress path, and if channel 6 is con - figured to operate in the dual-rail mode, then this input pin will func - tion as the "rxneg" (negative polarity data) input pin. in this case, the user should connect this particular input to the "rxneg" output pin of the corresponding ds3/e3/sts-1 liu channel. n ote : this pin is inactive if the pr imary frame synchronizer block (associated with channel 6) is not configured to operate in the ingress path. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 43 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ae19 sts3txa_dp_3 ing_lcv_in_7 ing_rxneg_in_7 txsts1pl_7 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus interface - parity input pin - channel 3, ds3/e3 framer bl ock lcv/rxneg input pin - chan - nel - channel 7: the function of this input pin depends upon whether or not the sts- 3/stm-1 telecom bus interface for channel 3 has been enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - transmit sts-3/stm-1 telecom bus interface - parity input pin: this input pin can be configured to function as one of the following. 1. the even or odd parity value of the bits which are input via the st3txa_d_3[7:0] input pins. 2. the even or odd parity value of the bits which are being input via the sts3txa_d_3[7:0] input and the states of the sts3txa_pl_3 and sts3txa_c1j1_3 input pins. n ote : any one of these configurati on selections can be made by writing the appropriate value into the interface control register - byte 3 register (indirect address = 0x00, 0x38), (direct address = 0x0138). if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3 framer block lcv/rxneg input pin - channel 7): if the sts-3/stm-1 telecom bus (channel 3) is disabled and if the ds3/e3 framer block (associated with channel 7) is enabled then this pin will function as either an lcv or an rxneg input pin. if channel 7 is configured to operate in the single-rail mode, and if the primary frame synchronizer block is configured to operate in the ingress path - ing_lcv_in_7 input pin: if the primary frame synchronizer bl ock (associated with channel 7) is configured to operate in the ingress path, and if channel 7 is con - figured to operate in the single-rail mode, then this input pin will function as the "lcv" (line code violation) input pin. in this case, the user should connect this particular input pin to the "lcv" output pin of the corresponding ds3/e3/sts-1 liu channel. if channel 7 is configured to operate in the dual-rail mode, and if the primary frame synchronizer block is configured to oper - ate in the ingress path - ing_rxneg_in_7: if the primary frame synchronizer bl ock (associated with channel 7) is configured to operate in the ingress path, and if channel 7 is con - figured to operate in the dual-rail mode, then this input pin will func - tion as the "rxneg" (negative polarity data) input pin. in this case, the user should connect this particular input to the "rxneg" output pin of the corresponding ds3/e3/sts-1 liu channel. n ote : this pin is inactive if the pr imary frame synchronizer block (associated with channel 7) is not configured to operate in the ingress path. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 44 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper b18 sts3txa_alarm_0 ing_lcv_in_0 ing_rxneg_in_0 txsts1pl_0 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus - alarm indicator input - channel 0; ds3/e3 framer block lcv/rxneg input pin - chan - nel 0: the function of this input pin depends upon whether or not the sts- 3/stm-1 telecom bus interface for channel 0 has been enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - transmit sts-3/stm-1 telecom bus interface - alarm indicator input: this input pin pulses "high" coincident to any sts-1 signal (which is carrying the ais-p indicator) being applied to the sts3txa_d_0[7:0] input data bus. n ote : if the sts3txa_alarm_0 input signal pulses "high" for any given sts-1 signal (within the incoming sts-3), then the xrt94l43 will automatically decla re an ais-p for that sts-1 channel. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3 framer block lcv/rxneg input pin - channel 0): if the sts-3/stm-1 telecom bus (channel 0) is disabled and if the ds3/e3 framer block (associated with channel 0) is enabled then this pin will function as either an lcv or an rxneg input pin. if channel 0 is configured to operate in the single-rail mode, and if the primary frame synchronizer block is configured to operate in the ingress path - ing_lcv_in_0 input pin if the primary frame synchronizer bl ock (associated with channel 0) is configured to operate in the ingress path, and if channel 0 is con - figured to operate in the single-rail mode, then this input pin will function as the "lcv" (line code violation) input pin. in this case, the user should connect this particular input pin to the "lcv" output pin of the corresponding ds3/e3/sts-1 liu channel. if channel 7 is configured to operate in the dual-rail mode, and if the primary frame synchronizer block is configured to oper - ate in the ingress path - ing_rxneg_in_0: if the primary frame synchronizer bl ock (associated with channel 0) is configured to operate in the ingress path and if channel 0 is con - figured to operate in the dual-rail mode, then this input pin will func - tion as the "rxneg" (negative polarity data) input pin. in this case, the user should connect this particular input to the "rxneg" output pin of the corresponding ds3/e3/sts-1 liu channel n ote : this pin is inactive if the pr imary frame synchronizer block (associated with channel 0) is not configured to operate in the ingress path. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 45 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 d25 sts3txa_alarm_1 ing_lcv_in_1 ing_rxneg_in_1 txsts1pl_1 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus - alarm indicator input - channel 1; ds3/e3 framer block lcv/rxneg input pin - chan - nel 1: the function of this input pin depends upon whether or not the sts- 3/stm-1 telecom bus interface for channel 1 has been enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - transmit sts-3/stm-1 telecom bus interface - alarm indicator input: this input pin pulses "high" coincident to any sts-1 signal (which is carrying the ais-p indicator) being applied to the sts3txa_d_1[7:0] input data bus. n ote : if the sts3txa_alarm_1 input signal pulses "high" for any given sts-1 signal (within the incoming sts-3), then the xrt94l43 will automatically decla re an ais-p for that sts-1 channel. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3 framer block lcv/rxneg input pin - channel 1): if the sts-3/stm-1 telecom bus (channel 1) is disabled and if the ds3/e3 framer block (associated with channel 1) is enabled then this pin will function as either an lcv or an rxneg input pin. if channel 1 is configured to operate in the single-rail mode, and if the primary frame synchronizer block is configured to operate in the ingress path - ing_lcv_in_1 input pin: if the primary frame synchronizer bl ock (associated with channel 1) is configured to operate in the ingress path, and if channel 1 is con - figured to operate in the single-rail mode, then this input pin will function as the "lcv" (line code violation) input pin. in this case, the user should connect this particular input pin to the "lcv" output pin of the corresponding ds3/e3/sts-1 liu channel. if channel 1 is configured to operate in the dual-rail mode, and if the primary frame synchronizer block is configured to oper - ate in the ingress path - ing_rxneg_in_1: if the primary frame synchronizer bl ock (associated with channel 1) is configured to operate in the ingress path and if channel 1 is con - figured to operate in the dual-rail mode, then this input pin will func - tion as the "rxneg" (negative polarity data) input pin. in this case, the user should connect this particular input to the "rxneg" output pin of the corresponding ds3/e3/sts-1 liu channel. n ote : this pin is inactive if the pr imary frame synchronizer block (associated with channel 1) is not configured to operate in the ingress path sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 46 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ab26 sts3txa_alarm_2 ing_lcv_in_2 ing_rxneg_in_2 txsts1pl_2 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus - alarm indicator input - channel 2; ds3/e3 framer block lcv/rxneg input pin - chan - nel 2: the function of this input pin depends upon whether or not the sts- 3/stm-1 telecom bus interface for channel 2 has been enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - transmit sts-3/stm-1 telecom bus interface - alarm indicator input: this input pin pulses "high" coincident to any sts-1 signal (which is carrying the ais-p indicator) being applied to the sts3txa_d_2[7:0] input data bus. n ote : if the sts3txa_alarm_2 input signal pulses "high" for any given sts-1 signal (within the incoming sts-3), then the xrt94l43 will automatically decla re an ais-p for that sts-1 channel. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3 framer block lcv/rxneg input pin - channel 2): if the sts-3/stm-1 telecom bus (channel 2) is disabled and if the ds3/e3 framer block (associated with channel 2) is enabled then this pin will function as either an lcv or an rxneg input pin. if channel 2 is configured to operate in the single-rail mode, and if the primary frame synchronizer block is configured to operate in the ingress path - ing_lcv_in_2 input pin: if the primary frame synchronizer bl ock (associated with channel 2) is configured to operate in the ingress path, and if channel 2 is con - figured to operate in the single-rail mode, then this input pin will function as the "lcv" (line code violation) input pin. in this case, the user should connect this particular input pin to the "lcv" output pin of the corresponding ds3/e3/sts-1 liu channel. if channel 2 is configured to operate in the dual-rail mode, and if the primary frame synchronizer block is configured to oper - ate in the ingress path - ing_rxneg_in_2: if the primary frame synchronizer bl ock (associated with channel 2) is configured to operate in the ingress path and if channel 2 is con - figured to operate in the dual-rail mode, then this input pin will func - tion as the "rxneg" (negative polarity data) input pin. in this case, the user should connect this particular input to the "rxneg" output pin of the corresponding ds3/e3/sts-1 liu channel. n ote : this pin is inactive if the pr imary frame synchronizer block (associated with channel 2) is not configured to operate in the ingress path. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 47 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 af22 sts3txa_alarm_3 ing_lcv_in_3 ing_rxneg_in_3 txsts1pl_3 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus - alarm indicator input - channel 3; ds3/e3 framer block lcv/rxneg input pin - chan - nel 3: the function of this input pin de pends upon whether or not the sts- 3/stm-1 telecom bus interface for channel 3 has been enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - transmit sts-3/stm-1 telecom bus interface - alarm indicator input: this input pin pulses "high" coincident to any sts-1 signal (which is carrying the ais-p indicator) being applied to the sts3txa_d_3[7:0] input data bus. n ote : if the sts3txa_alarm_3 input signal pulses "high" for any given sts-1 signal (within the incoming sts-3), then the xrt94l43 will automatically decla re an ais-p for that sts-1 channel. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3 framer block lcv/rxneg input pin - channel 3): if the sts-3/stm-1 telecom bus (channel 3) is disabled and if the ds3/e3 framer block (associated with channel 3) is enabled then this pin will function as either an lcv or an rxneg input pin. if channel 3 is configured to operate in the single-rail mode, and if the primary frame synchronizer block is configured to operate in the ingress path - ing_lcv_in_3 input pin: if the primary frame syncronizer block (associated with channel 3) is configured to operate in the ingress path, and if channel 3 is con - figured to operate in the single-rail mode, then this input pin will function as the "lcv" (line code violation) input pin. in this case, the user should connect this particular input pin to the "lcv" output pin of the corresponding ds3/e3/sts-1 liu channel. if channel 3 is configured to operate in the dual-rail mode, and if the primary frame synchronizer block is configured to oper - ate in the ingress path - ing_rxneg_in_3: if the primary frame synchronizer bl ock (associated with channel 3) is configured to operate in the ingress path and if channel 3 is con - figured to operate in the dual-rail mode, then this input pin will func - tion as the "rxneg" (negative polarity data) input pin. in this case, the user should connect this particular input to the "rxneg" output pin of the corresponding ds3/e3/sts-1 liu channel. n ote : this pin is inactive if the frame generator block, associated with channel 3 is by-passed sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 48 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper c15 sts3txa_d_0_0 txsbdata_0 rloop_0 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus - channel 0 - input data bus pin number 0/rloop_0 (general purpose) output pin: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - transmit sts-3/stm-1 telecom bus interface - input data bus pin number 0: this input pin along with sts3txa_ d_0[7:1] function as the sts-3/ stm-1 transmit (add) telecom bus - input data bus for channel 0. this input pin functions as the lsb (least significant bit) input pin on the transmit (add) telecom bus - input data bus. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_0. the lsb of any byte, which is being input into the sts-3/stm-1 transmit telecom bus - data bus (for channel 0) should be input via this pin. if sts-3/stm-1 telecom bus (chann el 0) is disabled - rloop_0 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropri - ate value into bit 1 (rloop) within the line interface drive register associated with channel 0 (indirect address = 0x1e, 0x80), (direct address = 0x1f80). n ote : for product legacy purposes, this pin is called rloop_0 because one possible application is to tie this output pin to an rloop (remote loop-back) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 49 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 c16 sts3txa_d_0_1 txsbdata_1 req_0 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus - channel 0 - input data bus pin number 0/req_0 (general purpose) output pin: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 1: this input pin along with sts3txa_d_0[7:2] and sts3txa_d_0_0 function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 0. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - req_0 (general purpose) output pin . this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropri - ate value into bit 5 (reqb) within the line interface drive register associated with channel 0 (indirect address = 0x1e, 0x80), (direct address = 0x1f01). n ote : for product legacy purposes, this pin is called req_0 because one possible application is to tie this output pin to an reqb (receive equalizer by-pass) or reqen (receive equalizer enable) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 50 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper b19 sts3txa_d_0_2 txsbdata_2 ds3/e3/ sts1_data_in_0 i ttl transmit sts-3/stm-1 telecom bus - channel 0 - input data bus pin number 2/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 0: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 2: sts3txa_d_0_2 this input pin along with sts3txa_d_0[7:3] and sts3txa_d_0[1:0] function as the sts-3/stm-1 transmit (add) telecom bus - input data bus for channel 0. the sts-3/stm-1 tele - com bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 0: this input accepts single-rail, re covered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 0). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_0 signal pin number f15. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_0 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 0 (indirect address = 0x1e, 0x01), (direct address = 0x1f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_0 signal upon the rising edge of ds3/e3/ sts1_clk_in_0. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 51 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 b23 sts3txa_d_0_3 txsbdata_3 ds3/e3/ sts1_data_in_4 i ttl transmit sts-3/stm-1 telecom bus - channel 0 - input data bus pin number 3/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 4: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 2: sts3txa_d_0_3: this input pin along with sts3txa_ d_0[7:4] and sts3txa_d_0[2:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 0. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 4: this input accepts single-rail, recovered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 4). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_4 signal pin number a22. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_4 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 4 (indirect address = 0x5e, 0x01), (direct address = 0x5f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_4 signal upon the rising edge of ds3/e3/ sts1_clk_in_4. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 52 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper b25 sts3txa_d_0_4 txsbdata_4 ds3/e3/ sts1_data_in_8 i ttl transmit sts-3/stm-1 telecom bus - channel 0 - input data bus pin number 3/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 4: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 4: sts3txa_d_0_4: this input pin along with sts3txa_ d_0[7:5] and st s3txa_d_0[3:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 0. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 8: this input accepts single-rail, re covered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 8). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_8 signal pin number a24. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_8 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 8 (indirect address = 0x9e, 0x01), (direct address = 0x9f01) to a "1". for sts-1 applications: the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_8 signal upon the rising edge of ds3/e3/ sts1_clk_in_8. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 53 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 f15 sts3txa_d_0_5 txsbdata_5 ds3/e3/ sts1_clk_in_0 i ttl transmit sts-3/stm-1 telecom bus - channel 0 - input data bus pin number 5/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 0: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 5: sts3txa_d_0_5: this input pin along with sts3txa_d_0[7:6] and sts3txa_d_0[4:0] function as the sts-3/stm-1 transmit (add) telecom bus - input data bus for channel 0. the sts-3/stm-1 tele - com bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 0: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 0). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_0 input pin number b19. by default, the data that is appl ied to the ds3/e3/sts1_data_in_0 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_0 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 0 (indirect address = 0x1e, 0x01)," (direct address = 0x1f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_0 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 54 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper a22 sts3txa_d_0_6 txsbdata_6 ds3/e3/ sts1_clk_in_4 i ttl transmit sts-3/stm-1 telecom bus - channel 0 - input data bus pin number 6/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 4: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 6: sts3txa_d_0_6: this input pin along with sts3 txa_d_0_7 and sts3txa_d_0[5:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 0. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 4: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 4). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/s ts1_data_in_4 input pin number b23. by default, the data that is appl ied to the ds3/e3/sts1_data_in_4 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_4 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 4 (indirect address = 0x5e, 0x01), (direct address = 0x5f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_4 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 55 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 a24 sts3txa_d_0_7 txsb_data_7 ds3/e3/ sts1_clk_in_8 i ttl transmit sts-3/stm-1 telecom bus - channel 0 - input data bus pin number 7/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 8: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with sts-3/stm-1 chan - nel 0 is enabled. if sts-3/stm-1 telecom bus (s ts-3/stm-1 - channel 0) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin number 7: sts3txa_d_0_7: this input pin along with sts3tx a_d_0[6:0] function as the sts-3/ stm-1 transmit (add) telecom bus - input data bus for channel 0. the sts-3/stm-1 telecom bus inte rface will sample and latch this pin upon the falling edge of sts3txa_clk_0. n ote : this input pin functions as the msb (most significant bit) of the transmit (add) telecom bus, for channel 0. if sts-3/stm-1 telecom bus (sts -3/stm-1 - channel 0) is dis - abled - ds3/e3/sts1_clk_in - ds3/e3/sts-1 line interface clock input - channel 8: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 8). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_8 input pin number b25. by default, the data that is appl ied to the ds3/e3/sts1_data_in_8 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_8 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 8 (indirect address = 0x9e, 0x01), " (direct address = 0x9f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_8 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 56 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper c25 sts3txa_d_1_0 txsbdata_0 rloop_1 i/o ttl transmit sts-3/stm-1 telecom bus - channel 1 - input data bus pin number 0/rloop_1 (general purpose) output pin: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 0: this input pin along with sts3txa_ d_1[7:1] function as the sts-3/ stm-1 transmit (add) telecom bus - input data bus for channel 1. this input pin functions as the lsb (least significant bit) input pin on the transmit (add) telecom bus - input data bus. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_1. the lsb of any byte, which is being input into the sts-3/stm-1 transmit telecom bus - data bus (for channel 1) should be input via this pin. if sts-3/stm-1 telecom bus (chann el 1) is disabled - rloop_1 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropri - ate value into bit 1 (rloop) within the line interface drive register associated with channel 1 (indirect address = 0x2e, 0x80), (direct address = 0x2f80). n ote : for product legacy purposes, this pin is called rloop_1 because one possible application is to tie this output pin to an rloop (remote loop-back) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 57 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 b26 sts3txa_d_1_1 txsbdata_1 req_1 i/o ttl transmit sts-3/stm-1 telecom bus - channel 1 - input data bus pin number 1/req_1 (general purpose) output pin: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 1: this input pin along with sts3txa_d_1[7:2] and sts3txa_d_1_0 function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 1. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - req_1 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropri - ate value into bit 5 (reqb) within the line interface drive register associated with channel 1 (indirect address = 0x2e, 0x80), (direct address = 0x2f80). n ote : for product legacy purposes, this pin is called req_1 because one possible application is to tie this output pin to an reqb (receive equalizer by-pass) or reqen (receive equalizer enable) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 58 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper e26 sts3txa_d_1_2 txsbdata_2 ds3/e3/ sts1_data_in_1 i ttl transmit sts-3/stm-1 telecom bus - channel 1 - input data bus pin number 2/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 1: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 2: sts3txa_d_1_2: this input pin along with sts3txa_d_1[7:3] and sts3txa_d_1[1:0] function as the sts-3/stm-1 transmit (add) telecom bus - input data bus for channel 1. the sts-3/stm-1 tele - com bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 1: this input accepts single-rail, re covered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 1). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_1 signal pin number d26. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_1 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 1 (indirect address = 0x2e, 0x01), (direct address = 0x2f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_1 signal upon the rising edge of ds3/e3/ sts1_clk_in_1. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 59 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 g24 sts3txa_d_1_3 txsbdata_3 ds3/e3/ sts1data_in_5 i ttl transmit sts-3/stm-1 telecom bus - channel 1 - input data bus pin number 3/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 5: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 3: sts3txa_d_1_3: this input pin along with sts3txa_ d_1[7:4] and sts3txa_d_1[2:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 1. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 5: this input accepts single-rail, recovered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 5). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_5 signal pin number f23. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_5 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 5 (indirect address = 0x6e, 0x01), (direct address = 0x6f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_5 signal upon the rising edge of ds3/e3/ sts1_clk_in_5. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 60 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper j24 sts3txa_d_1_4 txsbdata_4 ds3/e3/ sts1_data_in_9 i ttl transmit sts-3/stm-1 telecom bus - channel 1 - input data bus pin number 4/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 9: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 4: sts3txa_d_1_4: this input pin along with sts3txa_d_1[7:5] and sts3txa_d_1[3:0] function as the sts-3/stm-1 transmit (add) telecom bus - input data bus for channel 1. the sts-3/stm-1 tele - com bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 9: this input accepts single-rail, re covered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 9). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_9 signal pin number h23. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_9 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 9 (indirect address = 0xae, 0x01), (direct address = 0xaf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_9 signal upon the rising edge of ds3/e3/ sts1_clk_in_9. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 61 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 d26 sts3txa_d_1_5 ds3/e3/ sts1_clk_in_1 txsbdata_5 i ttl transmit sts-3/stm-1 telecom bus - channel 1 - input data bus pin number 5/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 1: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 5: sts3txa_d_1_5: this input pin along with sts3txa_ d_1[7:6] and sts3txa_d_1[4:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 1. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 1: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 1). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_1 input pin num - ber e26. by default, the data that is appl ied to the ds3/e3/sts1_data_in_1 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_1 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 1 (indirect address = 0x2e, 0x01), (direct address = 0x2f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_1 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 62 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper f23 sts3txa_d_1_6 ds3/e3/ sts1_clk_in_5 txsbdata_6 i ttl transmit sts-3/stm-1 telecom bus - channel 1 - input data bus pin number 6/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 5: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 6: sts3txa_d_1_6: this input pin along with sts3txa_d_1_7 and sts3txa_d_1[5:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 1. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 5: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 5). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_5 input pin num - ber g24. by default, the data that is appl ied to the ds3/e3/sts1_data_in_5 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_5 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 5 (indirect address = 0x6e, 0x01), (direct address = 0x6f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_5 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 63 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 h23 sts3txa_d_1_7 ds3/e3/ sts1_clk_in_9 txsbdata_7 i ttl transmit sts-3/stm-1 telecom bus - channel 1 - input data bus pin number 7/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 9: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 7: sts3txa_d_1_7: this input pin along with sts3tx a_d_1[6:0] function as the sts-3/ stm-1 transmit (add) telecom bus - input data bus for channel 1. the sts-3/stm-1 telecom bus inte rface will sample and latch this pin upon the falling edge of sts3txa_clk_1. n ote : this input pin functions as the msb (most significant bit) of the transmit (add) telecom bus, for channel 1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 9: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 9). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_9 input pin num - ber j24. by default, the data that is appl ied to the ds3/e3/sts1_data_in_9 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_9 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 9 (indirect address = 0xae, 0x01), " (direct address = 0xaf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_9 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 64 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ad26 sts3txa_d_2_0 rloop_2 txsbdata_0 i/o ttl transmit sts-3/stm-1 telecom bus - channel 2 - input data bus pin number 0/rloop_2 (general purpose) output pin: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 0: this input pin along with sts3txa_ d_2[7:1] function as the sts-3/ stm-1 transmit (add) telecom bus - input data bus for channel 2. this input pin functions as the lsb (least significant bit) input pin on the transmit (add) telecom bus - input data bus. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_2. the lsb of any byte, which is being input into the sts-3/stm-1 transmit telecom bus - data bus (for channel 2) should be input via this pin. if sts-3/stm-1 telecom bus (chann el 2) is disabled - rloop_2 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropri - ate value into bit 1 (rloop) within the line interface drive register associated with channel 2 (indirect address = 0x3e, 0x80), (direct address = 0x3f80). n ote : for product legacy purposes, this pin is called rloop_2 because one possible application is to tie this output pin to an rloop (remote loop-back) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 65 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ae26 sts3txa_d_2_1 req_2 txsbdata_1 i/o ttl transmit sts-3/stm-1 telecom bus - channel 2 - input data bus pin number 1/req_2 (general purpose) output pin: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 1: this input pin along with sts3txa_d_2[7:2] and sts3txa_d_2_0 function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 2. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - req_2 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropri - ate value into bit 5 (reqb) within the line interface drive register associated with channel 2 (indirect address = 0x3e, 0x80), (direct address = 0x3f80). n ote : for product legacy purposes, this pin is called req_2 because one possible application is to tie this output pin to an reqb (receive equalizer by-pass) or reqen (receive equalizer enable) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 66 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper v24 sts3txa_d_2_2 ds3/e3/ sts1_data_in_2 txsbdata_2 i ttl transmit sts-3/stm-1 telecom bus - channel 2 - input data bus pin number 2/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 2: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 2: sts3txa_d_2_2: this input pin along with sts3txa_d_2[7:3] and sts3txa_d_2[1:0] function as the sts-3/stm-1 transmit (add) telecom bus - input data bus for channel 2. the sts-3/stm-1 tele - com bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 2: this input accepts single-rail, re covered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 2). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_2 signal pin number v25. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_2 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 2 (indirect address = 0x3e, 0x01), (direct address = 0x3f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_2 signal upon the rising edge of ds3/e3/ sts1_clk_in_2. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 67 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ad24 sts3txa_d_2_3 ds3/e3/ sts1_data_in_6 txsbdata_3 i ttl transmit sts-3/stm-1 telecom bus - channel 2 - input data bus pin number 3/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 6: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 3: sts3txa_d_2_3: this input pin along with sts3txa_ d_2[7:4] and sts3txa_d_2[2:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 2. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 6: this input accepts single-rail, recovered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 6). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_6 signal pin number y22. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_6 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 6 (indirect address = 0x7e, 0x01), (direct address = 0x7f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_6 signal upon the rising edge of ds3/e3/ sts1_clk_in_6. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 68 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper af25 sts3txa_d_2_4 ds3/e3/ sts1_data_in_10 txsbdata_4 i ttl transmit sts-3/stm-1 telecom bus - channel 2 - input data bus pin number 4/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 10: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 4: sts3txa_d_2_4: this input pin along with sts3txa_ d_2[7:5] and st s3txa_d_2[3:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 2. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 line interface data input - channel 10: this input accepts single-rail, re covered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 10). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/ sts1_clk_in_10 signal pin number ab22. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_10 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 10 (indirect address = 0xbe, 0x01), (direct address = 0xbf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_10 signal upon the rising edge of ds3/e3/ sts1_clk_in_10. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 69 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 v25 sts3txa_d_2_5 ds3/e3/ sts1_clk_in_2 txsbdata_5 i ttl transmit sts-3/stm-1 telecom bus - channel 2 - input data bus pin number 5/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 2: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 5: sts3txa_d_2_5: this input pin along with sts3txa_ d_2[7:6] and sts3txa_d_2[4:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 2. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 2: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 2). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_2 input pin num - ber v24. by default, the data that is appl ied to the ds3/e3/sts1_data_in_2 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_2 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 2 (indirect address = 0x3e, 0x01), (direct address = 0x3f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_2 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 70 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper y22 sts3txa_d_2_6 ds3/e3/ sts1_clk_in_6 txsbdata_6 i ttl transmit sts-3/stm-1 telecom bus - channel 2 - input data bus pin number 6/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 6: the function of this pin depends upon whether or not the sts-3/ stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 6: sts3txa_d_2_6: this input pin along with sts3txa_d_2_7 and sts3txa_d_2[5:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 2. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 6: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 6). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_6 input pin num - ber ad24. by default, the data that is appl ied to the ds3/e3/sts1_data_in_6 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_6 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 6 (indirect address = 0x7e, 0x01), (direct address = 0x7f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_6 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 71 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ab22 sts3txa_d_2_7 ds3/e3/ sts1_clk_in_10 txsbdata_7 i ttl transmit sts-3/stm-1 telecom bus - channel 2 - input data bus pin number 7/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 10: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 7: sts3txa_d_2_7: this input pin along with sts3txa_ d_2[6:0] function as the sts-3/ stm-1 transmit (add) telecom bus - input data bus for channel 2. the sts-3/stm-1 telecom bus inte rface will sample and latch this pin upon the falling edge of sts3txa_clk_2. n ote : this input pin functions as the msb (most significant bit) of the transmit (add) telecom bus, for channel 2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 10: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 10). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_10 input pin number af25. by default, the data that is applied to the ds3/e3/ sts1_data_in_10 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_10 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 10 (indirect address = 0xbe, 0x01), (direct address = 0xbf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_10 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 72 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ac18 sts3txa_d_3_0 rloop_3 txsbdata_0 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus - channel 3 - input data bus pin number 0/rloop_3 general purpose) output pin: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 0: this input pin along with sts3txa_ d_3[7:1] function as the sts-3/ stm-1 transmit (add) telecom bus - input data bus for channel 3. this input pin functions as the lsb (least significant bit) input pin on the transmit (add) telecom bus - input data bus. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_3. the lsb of any byte, which is being input into the sts-3/stm-1 transmit telecom bus - data bus (for channel 3) should be input via this pin. if sts-3/stm-1 telecom bus (chann el 3) is disabled - rloop_3 (general purpose) output pin. this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropri - ate value into bit 1 (rloop) within the line interface drive register associated with channel 3 (indirect address = 0x4e, 0x80), (direct address = 0x4f80). n ote : for product legacy purposes, this pin is called rloop_3 because one possible application is to tie this output pin to an rloop (remote loop-back) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 73 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ab18 sts3txa_d_3_1 req_3 txsbdata_1 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus - channel 3 - input data bus pin number 1/req_3 (general purpose) output pin: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 1: this input pin along with sts3txa_d_3[7:2] and sts3txa_d_3_0 function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 3. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - req_3 (general purpose) output pin. this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropri - ate value into bit 5 (reqb) within the line interface drive register associated with channel 3 (indirect address = 0x4e, 0x80), (direct address = 0x4f80). n ote : for product legacy purposes, this pin is called req_3 because one possible application is to tie this output pin to an reqb (receive equalizer by-pass) or reqen (receive equalizer enable) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 74 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper aa20 sts3txa_d_3_2 ds3/e3/ sts1_data_in_3 txsbdata_2 i ttl transmit sts-3/stm-1 telecom bus - channel 3 - input data bus pin number 2/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 3: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 2: sts3txa_d_3_2: this input pin along with sts3txa_ d_3[7:3] and st s3txa_d_3[1:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 3. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 3: this input accepts single-rail, re covered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 3). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_3 signal pin number ad22. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_3 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 3 (indirect address = 0x4e, 0x01), (direct address = 0x4f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_3 signal upon the rising edge of ds3/e3/ sts1_clk_in_3. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 75 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ab19 sts3txa_d_3_3 ds3/e3/ sts1_data_in_7 txsbdata_3 i ttl transmit sts-3/stm-1 telecom bus - channel 3 - input data bus pin number 3/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 7: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 3: sts3txa_d_3_3: this input pin along with sts3txa_d_3[7:4] and sts3txa_d_3[2:0] function as the sts-3/stm-1 transmit (add) telecom bus - input data bus for channel 3. the sts-3/stm-1 tele - com bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 7: this input accepts single-rail, recovered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 7). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_7 signal pin number aa19. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_7 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 7 (indirect address = 0x8e, 0x01), (direct address = 0x8f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_7 signal upon the rising edge of ds3/e3/ sts1_clk_in_7. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 76 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ad16 sts3txa_d_3_4 ds3/e3/ sts1_data_in_11 txsbdata_4 i ttl transmit sts-3/stm-1 telecom bus - channel 3 - input data bus pin number 4/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 11 (ds3/e3/ sts1_data_in_11): the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 4: sts3txa_d_3_4: this input pin along with sts3txa_d_3[7:5] and sts3txa_d_3[3:0] function as the sts-3/stm-1 transmit (add) telecom bus - input data bus for channel 3. the sts-3/stm-1 tele - com bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 11: this input accepts single-rail, re covered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 11). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/ sts1_clk_in_11 signal pin number ab16. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_11 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 11 (indirect address = 0xce, 0x01), (direct address = 0xcf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_11 signal upon the rising edge of ds3/e3/ sts1_clk_in_11. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 77 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ad22 sts3txa_d_3_5 ds3/e3/ sts1_clk_in_3 txsbdata_5 i ttl transmit sts-3/stm-1 telecom bus - channel 3 - input data bus pin number 5/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 3: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 5: sts3txa_d_3_5: this input pin along with sts3txa_d_3[7:6] and sts3txa_d_3[4:0] function as the sts-3/stm-1 transmit (add) telecom bus - input data bus for channel 3. the sts-3/stm-1 tele - com bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 3: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 3). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_3 input pin num - ber aa20. by default, the data that is appl ied to the ds3/e3/sts1_data_in_3 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_3 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 3 (indirect address = 0x4e, 0x01), (direct address = 0x4f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_3 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 78 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper aa19 sts3txa_d_3_6 ds3/e3/ sts1_clk_in_7 txsbdata_6 i ttl transmit sts-3/stm-1 telecom bus - channel 3 - input data bus pin number 6/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 7: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 6: sts3txa_d_3_6: this input pin along with sts3 txa_d_3_7 and sts3txa_d_3[5:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 3. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 7: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 7). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_7 input pin num - ber ab19. by default, the data that is appl ied to the ds3/e3/sts1_data_in_7 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_7 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 7 (indirect address = 0x8e, 0x01), (direct address = 0x8f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_7 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 79 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ab16 sts3txa_d_3_7 ds3/e3/ sts1_clk_in_11 txsbdata_7 i ttl transmit sts-3/stm-1 telecom bus - channel 3 - input data bus pin number 7/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 11: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 7: sts3txa_d_3_7: this input pin along with sts3tx a_d_3[6:0] function as the sts-3/ stm-1 transmit (add) telecom bus - input data bus for channel 3. the sts-3/stm-1 telecom bus inte rface will sample and latch this pin upon the falling edge of sts3txa_clk_3. n ote : this input pin functions as the msb (most significant bit) of the transmit (add) telecom bus, for channel 3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 11: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 11). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/ e3/sts1_data_in_11 input pin num - ber ad16. by default, the data that is applie d to the ds3/e3/sts1_data_in_11 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_11 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 11 (indirect address = 0xce, 0x01), (direct address = 0xcf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_11 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 80 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ab25 txrefclk sse_pos o cmos transmit sts-3/stm-1 telecom bus reference clock output pin/slow-speed interface - egress - positive data i/o: the exact function of this pin depends upon whether or not thests- 3/stm-1 telecom bus is enabled, and whether the slow-speed interface is enabled. transmit sts-3/stm-1 telecom bus reference clock output pin: this pin generates a 19.44mhz clock signal that is ultimately derived from the clock synthesizer block (within the xrt9l43). if the user configures the sts-3/ stm-1 telecom bus interface to operate in the "re-phase off" mode, then the device (or entity) that is transmitting sts-3/stm-1 data (to the transmit sts-3/stm-1 telecom bus interface) must synch ronizes its data transmission to this output signal. the user is not required to use this signal if the sts-3/stm-1 tele - com bus interface has been configured to operate in the "re-phase on" mode. sse_pos (slow-speed interface - egress - port is enabled): if the slow-speed interface - egress (sse) port is enabled, then this pin will function as either the sse_pos output pin or the sse_pos input pin.if the user configures the sse port to operate in the "insert" mode, then the sse port will be configured to replace any "user- selected" egress ds3/e3 or st s-1 data-stream (within the xrt94l43) with the data that is applied to the sse_pos and sse_neg input pins. more specifically , in the "insert" mode, this pin will function as the "sse_pos" input pin. in this case, the sse port will sample and latch the contents of the input pin (along with the sse_neg, in a dual-rail manner) upon the falling edge of the sse_clk input clock signal. if the user configures the sse port to operate in the "extract" mode, then the sse port will output any "user-selected" egress ds3/e3 or sts-1 signal (within the xrt94l43) vi a this output port. more spe - cifically, in the "extract mode" this pin will function as the "sse_pos" output pin. in this case, the sse port will output data via this pin, along with the sse_pos output pin (in a dual-rail manner) upon the rising edge of the sse_ clk output signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 81 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 aa24 txsbfp_out ssi_neg o cmos transmit sts-3/stm-1 telecom bus framing pulse output pin: this pin generates a pulse at an 8khz rate. this signal is ultimately derived from the clock synthesizer block (within the xrt94l43). if the sts-3/stm-1 telecom bus interf ace is configured to operate in the "re-phase off" mode, then th e devices (or entities) that are transmitting sts-3/stm-1 data (to the transmit sts-3/stm-1 tele - com bus interface) mu st synchronize their sts-3/stm-1 frame transmission to this output signal. in the re-phase off mode, each device or entity must align their sts-3/stm-1 frame transmission to this signal, in order to insure that all four transmit sts-3/stm-1 telecom bus interfaces are pre - sented with toh data simultaneously. transmit sts-3/stm-1 telecom bus framing pulse output pin/ slow-speed interface - ingress - negative data i/o: the exact function of this pin depends upon whether or not thests- 3/stm-1 telecom bus is enabled and whether the slow-speed inter - face is enabled. transmit sts-3/stm-1 telecom bus framing pulse output pin: this pin generates a pulse at an 8khz rate. this signal is ultimately derived from the clock synthesizer block (within the xrt94l43). if the user configures the sts-3/ stm-1 telecom bus interface to operate in the "re-phase off" mode, then the devices (or entities) that is transmitting sts-3/stm-1 data (to the transmit sts-3/stm-1 telecom bus interface) must syn chronize its sts-3/stm-1 frame transmission to this output signal. in the re-phase off mode, each device or entity must align their sts-3/stm-1 frame transmission to this signal, in order to insure that all four transmit sts-3/stm-1 telecom bus interfaces are pre - sented with toh data simultaneously. ssi_neg (slow-speed interface - ingress port is enabled): if the slow-speed interface - ingress (ssi) port is enabled, then this pin will function as either the ssi_neg output pin or the ssi_neg input pin. if the user configures the ssi port to operate in the "insert" mode, then the ssi port will be configured to replace any "user-selected" ingress ds3/e3 or sts-1 data-stream (within the xrt94l43) with the data that is applied to the ssi_pos and ssi_neg input pins. more specifically, in the "insert" mode, this pin will function as the ssi_neg input pin. in this case, the ssi port will sample and latch the contents of this input pin (along with the ssi_pos input pin, in a dual-rail manner) upon the falling edge of the ssi_clk input clock signal. if the user configures the ssi port to operate in the "extract" mode, then the ssi port will output any "u ser-selected" ingress ds3/e3 or sts-1 signal (within the xrt94l43) vi a this output port. more spe - cifically, in the "extract mode" this pin will function as the "ssi_neg" output pin. in this case, the ssi po rt will output data via this pin, along with the ssi_pos output pin (in a dual-rail manner) upon the rising edge of the ssi_clk output signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 82 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper rxsts-1 toh/poh interface p in # s ignal n ame i/o s ignal t ype d escription a14 f20 k25 ad18 e16 h22 aa25 ac15 e19 k22 ad23 aa12 rxsts1ohsel_0 rxsts1ohsel_1 rxsts1ohsel_2 rxsts1ohsel_3 rxsts1ohsel_4 rxsts1ohsel_5 rxsts1ohsel_6 rxsts1ohsel_7 rxsts1ohsel_8 rxsts1ohsel_9 rxsts1ohsel_10 rxsts1ohsel_11 o cmos receive sts-1 toh and poh output port - poh data indicator: these output pins, along with rxsts1ohclk_n, rxsts1ohframe_n and rxsts1oh_n function as the receive sts-1 toh and poh output port. these output pins indicate whether poh or toh data is being output via the rxsts1oh_n output pins. these output pins will toggle "hig h" coincident with the poh data as it is being output via the rxsts1 oh_n output pins. conversely, these output pins will toggle "low " coincident with the toh data as it is being output via the rxsts1oh_n output pins. n ote : these output pins are updat ed upon the falling edge of rxsts1ohclk_n. as a consequence, external circuitry, receiving this data, should sample this data upon the rising edge of rxsts1ohclk_n. d11 g22 u23 ad20 b15 j21 aa26 af15 e17 k23 af26 ad11 rxsts1oh_0 rxsts1oh_1 rxsts1oh_2 rxsts1oh_3 rxsts1oh_4 rxsts1oh_5 rxsts1oh_6 rxsts1oh_7 rxsts1oh_8 rxsts1oh_9 rxsts1oh_10 rxsts1oh_11 o cmos receive sts-1 toh and poh output port - output pin: these output pins, along with rxsts1ohsel_n, rxsts1ohclk_n and rxsts1ohframe_n function as the receive sts-1 toh and poh output port. each bit, within the toh and poh bytes (within the incoming sts-1 data stream) is updated upon the falling edge of rxsts1ohclk_n. as a consequence, external circuitry receiving this data, should sam - ple this data upon the rising edge of rxsts1ohclk_n. n otes : 1. the external circuitry can determine whether or not it is receiving poh or toh data via this output pin. the rxsts1ohsel_n output pin will be "high" anytime poh data is being output via these output pins. conversely, the rxsts1ohsel_n output pin will be "low" anytime toh data is being output via these output pins. 2. toh and poh data, associated with receive sts-1 toh and poh processor block - channel 0 will be output via the rxsts1oh_0, and so on.
xrt94l43 83 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 f12 f22 t24 ae20 a18 h21 ab24 ae16 e18 k26 aa23 af10 rxsts1ohclk_0 rxsts1ohclk_1 rxsts1ohclk_2 rxsts1ohclk_3 rxsts1ohclk_4 rxsts1ohclk_5 rxsts1ohclk_6 rxsts1ohclk_7 rxsts1ohclk_8 rxsts1ohclk_9 rxsts1ohclk_10 rxsts1ohclk_11 o cmos receive sts-1 toh and poh output port - clock output signal: these output pins, along with rxsts1oh_n, rxsts1ohframe_n, and rxsts1ohsel_n function as the receive sts-1 toh and poh output port. these output pins function as the clock output signals for the receive sts-1 toh and poh ou tput port. the rxsts1oh_n, rxsts1frame_n and rxsts1ohsel_n output pins are updated upon the falling edge of this clock signal. d12 e22 u26 af18 b17 j22 w22 af12 f19 k24 af23 ad10 rxsts1ohframe_0 rxsts1ohframe_1 rxsts1ohframe_2 rxsts1ohframe_3 rxsts1ohframe_4 rxsts1ohframe_5 rxsts1ohframe_6 rxsts1ohframe_7 rxsts1ohframe_8 rxsts1ohframe_9 rxsts1ohframe_1 0 rxsts1ohframe_11 o cmos receive sts-1 toh and poh output port - frame boundary indicator: these output pins, along with rxsts1oh_n, rxsts1ohsel_n and rxsts1ohclk_n function as the receive sts-1 toh and poh output port. these output pins will pulse "high" coincident with either of the fol - lowing events. 1. when the very first toh byte (a1), of a given sts-1 frame, is being output via the corresponding rxsts1oh_n output pin. 2. when the very first poh byte (j1), of a given sts-1 frame, is being output via the corresponding rxsts1oh_n output pin. n ote : the external circuitry can det ermine whether these output pins are pulsing "high" for the first toh or poh byte by checking the state of the corresponding rxsts1ohsel_n output pin. rxsts-1 toh/poh interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 84 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper
xrt94l43 85 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 sts-3/stm-1 telecom bus inte rface - receive direction p in # s ignal n ame i/o s ignal t ype d escription a20 sts3rxd_clk_0 rxsbclklloop_0 o cmos receive sts-3/stm-1 telecom bus clock output - channel 0; lloop_0 (general purpose) output pin: the function of this input pin d epends upon whether or not thests-3/ stm-1 telecom bus interface associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/ stm-1 receive telecom bus clock output - channel 0; sts3rxd_clk_0: all signals, which is output via the receive telecom bus - channel 0 is clocked out upon the rising edge of th is clock signal. this includes the fol - lowing signals. ? sts3rxd_d_0[7:0] ? sts3rxd_alarm_0 ? sts3rxd_dp_0 ? sts3rxd_pl_0 ? sts3rxd_c1j1_0 this clock signal will operate at 19.44mhz. if sts-3/stm-1 telecom bus (channel 0) is disabled - lloop_0 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 0 (lloop) within the line interface drive register associ - ated with channel 0 (indirect address = 0x1e, 0x80), (direct address = 0x1f80). n ote : for product legacy purposes, this pin is called lloop_0 because one possible application is to tie this output pin to an lloop (local loop-back) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose.
xrt94l43 86 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper d23 sts3rxd_clk_1 rxsbclklloop_1 o cmos receive sts-3/stm-1 telecom bus clock output - channel 1; lloop_1 (general purpose) output pin: the function of this input pin d epends upon whether or not thests-3/ stm-1 telecom bus interface associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/ stm-1 receive telecom bus clock output - channel 1; sts3rxd_clk_1: all signals, which is output via the receive telecom bus - channel 1 is clocked out upon the rising edge of th is clock signal. this includes the fol - lowing signals. ? sts3rxd_d_1[7:0] ? sts3rxd_alarm_1 ? sts3rxd_dp_1 ? sts3rxd_pl_1 ? sts3rxd_c1j1_1 this clock signal will operate at 19.44mhz. if sts-3/stm-1 telecom bus (channel 1) is disabled - lloop_1 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 0 (lloop) within the line interface drive register associ - ated with channel 1 (indirect address = 0x2e, 0x80), (direct address = 0x2f80). n ote : for product legacy purposes, this pin is called lloop_1 because one possible application is to tie this output pin to an lloop (local loop-back) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 87 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 w23 sts3rxd_clk_2 rxsbclklloop_2 o cmos receive sts-3/stm-1 telecom bus clock output - channel 2; lloop_2 (general purpose) output pin: the function of this input pin d epends upon whether or not thests-3/ stm-1 telecom bus interface associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/ stm-1 receive telecom bus clock output - channel 2; sts3rxd_clk_2: all signals, which is output via the receive telecom bus - channel 2 is clocked out upon the rising edge of th is clock signal. this includes the fol - lowing signals. ? sts3rxd_d_2[7:0] ? sts3rxd_alarm_2 ? sts3rxd_dp_2 ? sts3rxd_pl_2 ? sts3rxd_c1j1_2 this clock signal will operate at 19.44mhz. if sts-3/stm-1 telecom bus (channel 2) is disabled - lloop_2 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 0 (lloop) within the line interface drive register associ - ated with channel 2 (indirect address = 0x3e, 0x80), (direct address = 0x3f80). n ote : for product legacy purposes, this pin is called lloop_2 because one possible application is to tie this output pin to an lloop (local loop-back) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 88 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper af20 sts3rxd_clk_3 rxsbclklloop_3 o cmos receive sts-3/stm-1 telecom bus clock output - channel 3; lloop_3 (general purpose) output pin: the function of this input pin d epends upon whether or not thests-3/ stm-1 telecom bus interface associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/ stm-1 receive telecom bus clock output - channel 3; sts3rxd_clk_3: all signals, which is output via the receive telecom bus - channel 3 is clocked out upon the rising edge of th is clock signal. this includes the fol - lowing signals. ? sts3rxd_d_3[7:0] ? sts3rxd_alarm_3 ? sts3rxd_dp_3 ? sts3rxd_pl_3 ? sts3rxd_c1j1_3 this clock signal will operate at 19.44mhz. if sts-3/stm-1 telecom bus (channel 3) is disabled - lloop_3 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 0 (lloop) within the line interface drive register associ - ated with channel 3 (indirect address = 0x4e, 0x80), (direct address = 0x4f80). n ote : for product legacy purposes, this pin is called lloop_3 because one possible application is to tie this output pin to an lloop (local loop-back) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 89 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 a21 sts3rxd_pl_0 taos_0 o cmos sts-3/stm-1 receive (drop) telecom bus - payload indicator out - put signal - channel 0/taos_0 (gen eral purpose) output pin - chan - nel 0: the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface block associated with channel 0 has been enabled or disabled. if the sts-3/stm-1 telecom bus interface (associated with channel 0) is enabled - sts-3/sts-1 receive (drop) telecom bus - payload indicator output - sts3rxd_pl_0: this output pin indicates whether or not transport overhead bytes are being output via the sts3rx d_d_0[7:0] output pins. this output pin is pulled "low" for the duration that the sts-3/stm-1 receive telecom bus is transmitting a transport overhead byte via the sts3rxd_d_0[7:0] output pins. conversely, this output pin is pulled "high" for the duration that the sts- 3/stm-1 receive telecom bus is tran smitting something other than a transport overhead byte via the sts3rxd_d_0[7:0] output pins. if the sts-3/stm-1 telecom bus interface (associated with channel 0) is disabled - taos_0 (general purpose) output pin - channel 0: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 4 (taos) within the li ne interface drive register associ - ated with channel 0 (indirect address = 0x1e, 0x80), (direct address = 0x1f80). n ote : for product legacy purposes, this pin is called taos_0 because one possible application is to tie this output pin to an taos (transmit all ones) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 90 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper d24 sts3rxd_pl_1 taos_1 o cmos sts-3/stm-1 receive (drop) tel ecom bus - payload indicator out - put signal - channel 1/taos_1 (gen eral purpose) output pin - chan - nel 1: the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface block associated with channel 1 has been enabled or disabled. if the sts-3/stm-1 telecom bus interface (associated with channel 1) is enabled - sts-3/sts-1 receive (drop) telecom bus - payload indicator output - sts3rxd_pl_1: this output pin indicates whether or not transport overhead bytes are being output via the sts3rx d_d_1[7:0] output pins. this output pin is pulled "low" for the duration that the sts-3/stm-1 receive telecom bus is transmitting a transport overhead byte via the sts3rxd_d_1[7:0] output pins. conversely, this output pin is pulled "high" for the duration that the sts- 3/stm-1 receive telecom bus is tran smitting something other than a transport overhead byte via the sts3rxd_d_1[7:0] output pins. if the sts-3/stm-1 telecom bus interface (associated with channel 1) is disabled - taos_1 (general purpose) output pin - channel 1: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 4 (taos) within the li ne interface drive register associ - ated with channel 1 (indirect address = 0x2e, 0x80), (direct address = 0x2f80). n ote : for product legacy purposes, this pin is called taos_1 because one possible application is to tie this output pin to an taos (transmit all ones) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 91 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 v23 sts3rxd_pl_2 taos_2 o cmos sts-3/stm-1 receive (drop) telecom bus - payload indicator out - put signal - channel 2/taos_2 (gen eral purpose) output pin - chan - nel 2: the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface block associated with channel 2 has been enabled or disabled. if the sts-3/stm-1 telecom bus interface (associated with channel 2) is enabled - sts-3/sts-1 receive (drop) telecom bus - payload indicator output - sts3rxd_pl_2: this output pin indicates whether or not transport overhead bytes are being output via the sts3rx d_d_2[7:0] output pins. this output pin is pulled "low" for the duration that the sts-3/stm-1 receive telecom bus is transmitting a transport overhead byte via the sts3rxd_d_2[7:0] output pins. conversely, this output pin is pulled "high" for the duration that the sts- 3/stm-1 receive telecom bus is tran smitting something other than a transport overhead byte via the sts3rxd_d_2[7:0] output pins. if the sts-3/stm-1 telecom bus interface (associated with channel 2) is disabled - taos_2 (general purpose) output pin - channel 2: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 4 (taos) within the li ne interface drive register associ - ated with channel 2 (indirect address = 0x3e, 0x80), (direct address = 0x3f80). n ote : for product legacy purposes, this pin is called taos_2 because one possible application is to tie this output pin to an taos (transmit all ones) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 92 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper af21 sts3rxd_pl_3 taos_3 o cmos sts-3/stm-1 receive (drop) tel ecom bus - payload indicator out - put signal - channel 3/taos_3 (gen eral purpose) output pin - chan - nel 3: the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface block associated with channel 3 has been enabled or disabled. if the sts-3/stm-1 telecom bus interface (associated with channel 3) is enabled - sts-3/sts-1 receive (drop) telecom bus - payload indicator output - sts3rxd_pl_3: this output pin indicates whether or not transport overhead bytes are being output via the sts3rx d_d_3[7:0] output pins. this output pin is pulled "low" for the duration that the sts-3/stm-1 receive telecom bus is transmitting a transport overhead byte via the sts3rxd_d_3[7:0] output pins. conversely, this output pin is pulled "high" for the duration that the sts- 3/stm-1 receive telecom bus is tran smitting something other than a transport overhead byte via the sts3rxd_d_3[7:0] output pins. if the sts-3/stm-1 telecom bus interface (associated with channel 3) is disabled - taos_3 (general purpose) output pin - channel 3: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 4 (taos) within the li ne interface drive register associ - ated with channel 3 (indirect address = 0x4e, 0x80), (direct address = 0x4f80) . n ote : for product legacy purposes, this pin is called taos_3 because one possible application is to tie this output pin to an taos (transmit all ones) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 93 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 c23 sts3rxd_c1j1_0 eg_ds3e3_fp_8 txsts1fp_8 rxsbframe_0 o cmos sts-3/stm-1 receive telecom bus - c1/j1 byte phase indicator output signal - channel 0; egress direction ds3/e3 frame genera - tor block framing pulse output pin - channel 8; transmit sts-1 framing pulse output pin - channel 8: the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface for sts-3/stm-1 channel 0 has been enabled. if sts-3/stm-1 telecom bus (asso ciatd with sts- 3/stm-1 channel 0) has been enabled - sts-3/stm-1 receive telecom bus - c1/j1 byte phase indicator output signal: this output pin pulses "high" under the following two conditions. 1. whenever the c1 byte is being output via the sts3rxd_d_0[7:0] out - put, and 2. whenever the j1 byte is being output via the sts3rxd_d_0[7:0] out - put.1: n otes : 1. the sts-3/stm-1 receive (dro p) telecom bus (associated with channel 0) will indicate that it is transmitting the c1 byte (via the sts3rxd_d_0[7:0] output pins), by pulsing this output pin "high" (for one period of sts3rxd_clk_0) and keeping the sts3rxd_pl_0 output pin pulled "low". 2. the sts-3/stm-1 receive (dro p) telecom bus (associated with channel 0) will indicate that it is transmitting the j1 byte (via the sts3rxd_d_0[7:0] ou tput pins), by pulsing this output pin "high" (for one period of sts3rxd_clk_0) while the sts3txd_pl_0 output pin is pulled "high". sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 94 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper c23 sts3rxd_c1j1_0 eg_ds3e3_fp_8 txsts1fp_8 rxsbframe_0 continued o cmos continued if sts-3/stm-1 telecom bus (assoc iated with sts- 3/stm-1 channel 0) is disabled then the function of this output pin depends upon whether channel 8 has been configured to operate in either the ds3/ e3 or sts-1 modes): if channel 8 is configured to operate in the ds3/e3 mode - eg_ds3e3_fp_8 (egress direction - ds3/e3 framing pulse output pin - channel 8): if the sts-3/stm-1 telecom bus (associated with sts-3/stm-1 channel 0) is disabled and if channel 8 is co nfigured to operate in either the ds3 or e3 modes then this pin will functi on as the "egress direction ds3/e3 framing pulse" output pin. in this mode, the frame generator block (associated with channel 8) will pulse this output pin "high" for one ds3/e3 bit-period, coincident with the first bit (within a given ds3 or e3 frame) being output via the "ds3/ e3/sts1_data_out_8" output pin. if channel 8 is configured to operate in the sts-1 mode - txsts1_fp_8 (transmit direction - sts-1 framing pulse output pin - channel 8): if the sts-3/stm-1 telecom bus (associated with sts-3/stm-1 channel 0) is disabled and if channel 8 is configured to operate in the sts-1/ stm-0 mode, then this pin will functi on as the "transmit direction sts-1 framing pulse" output pin .in this mode, the transmit sts-1 toh processor block (associated with channel 8) will pulse this output pi n "high" for one sts-1 bit-period, coincident to whenever the very fi rst bit (within a given sts-1 frame) being output via the "ds3/e3/sts1_data_out_8" output pin. n ote : for those applications in which the xrt94l43 is being interfaced to ds3/e3/sts-1 liu devices, we recommend that the user not connect this output pin to any liu input pin. j25 sts3rxd_c1j1_1 eg_ds3e3_fp_9 txsts1fp_9 rxsbframe_1 o cmos sts-3/stm-1 receive telecom bus - c1/j1 byte phase indicator output signal - channel 1; egress direction ds3/e3 frame genera - tor framing pulse output pin - channel 9; transmit sts-1 framing pulse output pin - channel 9: see description for pin # c23 above using the appropriate channel num - bers. if sts-3/stm-1 telecom bus (associated with sts-3/stm-1 has been enabled - sts-3/stm-1 receive telecom bus - c1/j1 byte phase indicator output signal: if sts-3/stm-1 telecom bus (assoc iated with sts- 3/stm-1 channel 1) is disabled then the function of this output pin depends upon whether channel 9 has been configured to in either the ds3/e3 or sts-1` modes: sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 95 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ac20 sts3rxd_c1j1_2 eg_ds3e3_fp_10 txsts1fp_10 rxsbframe_2 o cmos sts-3/stm-1 receive telecom bus - c1/j1 byte phase indicator output signal - channel 2; egress direction ds3/e3 frame genera - tor block framing pulse output pin - channel 11; transmit sts-1 framing pulse output pin - channel 10: see description for pin # c23 above using the appropriate channel num - bers. if sts-3/stm-1 telecom bus ((associ ated with sts-3/stm-1 channel 2) has been enabled - sts-3/stm-1 receive telecom bus - c1/j1 byte phase indicator output signal: if sts-3/stm-1 telecom bus ((associ ated with sts-3/stm-1 channel 2) is disabled - rxds3fp_10 (receive ds3 frame pulse input/out - put - channel 10): ae14 sts3rxd_c1j1_3 eg_ds3e3_fp_11 txsts1fp_11 rxsbframe_3 o cmos sts-3/stm-1 receive telecom bus - c1/j1 byte phase indicator output signal - channel 3; egress direction ds3/e3 frame genera - tor block framing pulse output pin - channel 11; transmit sts-1 framing pulse output pin - channel 11: see description for pin # c23 above using the appropriate channel num - bers. if sts-3/stm-1 telecom bus (asso ciated with sts-3/stm-1- chan - nel 2) is disabled then the function of this output pin depends upon whether channel 10 has been configured to operate in either the ds3/e3 or sts-1 modes.: if sts-3/stm-1 telecom bus (assoc iated with sts- 3/stm-1 channel 3) is disabled then the function of this output pin depends upon whether channel 11 has been configured to operate in either the ds3/e3 or sts-1 modes. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 96 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper c22 sts3rxd_dp_0 eg_ds3e3_fp_4 txsts1fp_4 o cmos sts-3/stm-1 receive (drop) telecom bus - parity output pin - channel 0; egress direction ds3/e3 frame generator block fram - ing pulse output pin - channel 4; transmit sts-1 framing pulse output pin - channel 4: the function of this output pin depends upon whether or not the sts-3/ stm-1 telecom bus interface for sts-3/stm-1 channel 0 has been enabled. if sts-3/stm-1 telecom bus (associated with sts-3/stm-1 channel 0) has been enabled - sts-3/stm-1 receive telecom bus - parity output pin: this output pin can be configured to function as one of the following. 1. the even or odd parity value of the bits which are output via the "sts3rxd_d_0[7:0]" output pins. 2. the even or odd parity value of the bits which are being output via the "sts3rxd_d_0[7:0]" outpu t pins and the states of the "sts3rxd_pl_0" and "sts3rxd_c1j1_0" output pins. this output pin will ultimately be used (by "drop-side" circuitry) to verify the verify of the data which is output via the "sts-3/stm-1 telecom bus interface associated with channel 0 n ote : the user can make any one of th ese configuration selections by writing the appropriate value into the "telecom bus control" register (direct address = 0x013b). if sts-3/stm-1 telecom bus (associated with sts-3/stm-1 channel 0) is disabled then the function of this output pin depends upon whether channel 4 has been configured to operat e in either the ds3/e3 or sts-1 modes if channel 4 is configured to operate in the ds3/e3 modes - eg_ds3e3_fp_4 (egress direction - ds3/e3 framing pulse output pin - channel 4): if the sts-3/stm-1 telecom bus (associated with sts-3/stm-1 channel 0) is disabled and if channel 4 is co nfigured to operate in either the ds3 or e3 modes then this pin will functi on as the "egress direction ds3/e3 framing pulse" output pin. in this mode, the frame generator block (associated with channel 4) will pulse this output pin "high" for one ds3/e3 bit-period, coincident with the first bit (within a given ds3 or e3 frame) being output via the "ds3/ e3/sts1_data_out_4" output pin. if channel 4 is configured to operate in the sts-1 mode - txsts1_fp_4 (transmit direction - sts-1 framing pulse output pin - channel 4): if the sts-3/stm-1 telecom bus (associated with sts-3/stm-1 channel 0) is disabled and if channel 4 is configured to operate in the sts-1/ stm-0 mode, then this pin will functi on as the "transmit direction sts-1 framing pulse" output pin. in this mode, the transmit sts-1 toh processor block (associated with channel 4) will pulse this output pi n "high" for one sts-1 bit-period, coincident to whenever the very fi rst bit (within a given sts-1 frame) being output via the "ds3/e3/sts1_data_out_4" output pin. n ote : for those applications in which the xrt94l43 is being interfaced to ds3/e3/sts-1 liu devices, we recommend that the user not connect this output pin to any liu input pin. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 97 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 g25 sts3rxd_dp_1 eg_ds3e3_fp_5 txsts1fp_5 o cmos sts-3/stm-1 receive (drop) telecom bus - parity output pin - channel 1; egress direction ds3/e3 frame generator block fram - ing pulse output pin - channel 5; transmit sts-1 framing pulse output pin - channel 5: see description for pin # c22 above using the appropriate channel num - bers. if sts-3/stm-1 telecom bus ((associ ated with sts-3/stm-1 channel 1) has been enabled - sts-3/stm-1 receive telecom bus - parity output pin: if sts-3/stm-1 telecom bus (assoc iated with sts- 3/stm-1 channel 1) is disabled then the function of this output pin depends upon whether channel 5 has been configured to operate in either the ds3/ e3 or sts-1 modeschannel 1) is disabled - rxds3fp_5 (receive ds3 frame pulse input/output - channel 5): ac23 sts3rxd_dp_2 eg_ds3e3_fp_6 txsts1fp_6 o cmos sts-3/stm-1 receive (drop) telecom bus - parity output pin - sts- 3/stm-1 channel 2; egress dir ection ds3/e3 frame generator block framing pulse output pin - channel 6; transmit sts-1 fram - ing pulse output pin - channel 6: see description for pin # c22 above using the appropriate channel num - bers. if sts-3/stm-1 telecom bus (assoc iated with sts- 3/stm-1 channel 2) has been enabled - sts-3/stm-1 receive telecom bus - parity output pin: if sts-3/stm-1 telecom bus (assoc iated with sts- 3/stm-1 channel 2) is disabled then the function of this output pin depends upon whether channel 2 has been configured to operate in either the ds3/ e3 or sts-1 modes: ac17 sts3rxd_dp_3 eg_ds3e3_fp_7 txsts1fp_7 o cmos sts-3/stm-1 receive (drop) telecom bus - parity output pin - sts- 3/stm-1 channel 3; egress dir ection ds3/e3 frame generator block framing pulse output pin - channel 7; transmit sts-1 fram - ing pulse output pin - channel 7: see description for pin # c22 above using the appropriate channel num - bers. if sts-3/stm-1 telecom bus ((associ ated with sts-3/stm-1 channel 3) has been enabled - sts-3/stm-1 receive telecom bus - parity output pin: if sts-3/stm-1 telecom bus (assoc iated with sts- 3/stm-1 channel 3) is disabled then the function of this output pin depends upon whether channel 7 has been configured to operate in either the ds3/ e3 or sts-1 modes: sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 98 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper c20 sts3rxd_alarm_0 eg_ds3e3_fp_0 txsts1fp_0 o cmos sts-3/stm-1 receive (drop) telecom bus - alarm indicator output signal - channel 0; egress direction ds3/e3 frame generator block framing pulse output pin - channel 0; transmit sts-1 framing pulse output pin - channel 0: this output pin pulses "high", coincident with any sts-1 signal (that is being output via the "sts3rxd_d_0[7:0] " output pins) that is carrying an ais-p indicator. this output pin is "low" for all other conditions. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/ stm-1 receive telecom bus - alarm indicator output signal: this output pin pulses "high", coincident with any sts-1 signal (that is being output via the "sts3rxd_d_0[7:0] " output pins) that is carrying an ais-p indicator. this output pin is "low" for all other conditions. if sts-3/stm-1 telecom bus (channel 0) is disabled then the func - tion of this output pin depends upon whether channel 0 has been configured to operate in either the ds3/e3 or sts-1 modes if channel 0 is configured to operate in the ds3/e3 modes - eg_ds3e3_fp_0 (egress direction - ds3/e3 framing pulse output pin - channel 0): if the sts-3/stm-1 telecom bus (channel 0) is disabled and if channel 0 is configured to operate in either th e ds3 or e3 modes then this pin will function as the "egress direction ds 3/e3 framing pulse" output pin. in this mode, the frame generator block (associated with channel 0) will pulse this output pin "high" for one ds3/e3 bit-period, coincident with the first bit (within a given ds3 or e3 frame) being output via the "ds3/ e3/sts1_data_out_0" output pin. if channel 3 is configured to operate in the sts-1 mode - txsts1_fp_3 (transmit direction - sts-1 framing pulse output pin - channel 3): if the sts-3/stm-1 telecom bus (channel 0) is disabled and if channel 0 is configured to operate in the sts-1/stm-0 mode, then this pin will function as the "transmit direction sts-1 framing pulse" output pin. in this mode, the transmit sts-1 toh processor block (associated with channel 0) will pulse this output pi n "high" for one sts-1 bit-period, coincident to whenever the very fi rst bit (within a given sts-1 frame) being output via the "ds3/e3/sts1_data_out_0" output pin. n ote : for those applications in which the xrt94l43 is being interfaced to ds3/e3/sts-1 liu devices, we recommend that the user not connect this output pin to any liu input pin. e25 sts3rxd_alarm_1 rxds3fp_1 txsts1fp_1 o cmos sts-3/stm-1 receive (drop) telecom bus - alarm indicator output signal - channel 1; ds3/e3 frame synchronizer framing pulse out - put pin - channel 1: see description for pin # c20 above using the appropriate channel num - bers. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/ stm-1 receive telecom bus - alarm indicator output signal: if sts-3/stm-1 telecom bus (channel 1) is disabled then the func - tion of this output pin depends upon whether channel 1 has been configured to operate in either the ds3/e3 or sts-1 modes sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 99 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 v21 sts3rxd_alarm_2 rxds3fp_2 txsts1fp_2 o cmos sts-3/stm-1 receive (drop) telecom bus - alarm indicator output signal - channel 2; ds3/e3 frame synchronizer framing pulse out - put pin - channel 2: see description for pin # c20 above using the appropriate channel num - bers. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/ stm-1 receive telecom bus - alarm indicator output signal: if sts-3/stm-1 telecom bus (channel 2) is disabled then the func - tion of this output pin depends upon whether channel 1 has been configured to operate in either the ds3/e3 or sts-1 modes ad21 sts3rxd_alarm_3 rxds3fp_3 txsts1fp_3 o cmos sts-3/stm-1 receive (drop) telecom bus - alarm indicator output signal - channel 3; ds3/e3 frame synchronizer framing pulse out - put pin - channel 1: see description for pin # c20 above using the appropriate channel num - bers. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/ stm-1 receive telecom bus - alarm indicator output signal: if sts-3/stm-1 telecom bus (channel 3) is disabled then the func - tion of this output pin depends upon whether channel 1 has been configured to operate in either the ds3/e3 or sts-1 modes b21 sts3rxd_d_0_0 txlev_0 rxsbdata_0 o cmos receive sts-3/stm-1 telecom bus - channel 0 - output data bus pin number 0/txlev_0 (general purpose) output pin: the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 0: stsrxd_d_0_0: this output pin along with sts3rxd_ d_0[7:1] function as the sts-3/ stm-1 receive (drop) telecom bus - output data bus for channel 0. the sts-3/stm-1 telecom bus interf ace will update the data via this output upon the rising edge of sts3rxd_clk_0. n ote : this input pin functions as the l sb (least significant bit) of the receive (drop) telecom bus for channel 0. if sts-3/stm-1 telecom bus (channel 0) is disabled - txlev_0 (general purpose) output pin. this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 2 (txlev) within the line interface drive register associ - ated with channel 0 (indirect address = 0x1e, 0x80), (direct address = 0x1f80). n ote : for product legacy purposes, this pin is called txlev_0 because one possible application is to tie this output pin to a txlev (transmit line build-out disable) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 100 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper b20 sts3rxd_d_0_1 encodis_0 rxsbdata_1 o cmos receive sts-3/stm-1 telecom bus - channel 0 - output data bus pin number 1/encodis_0 (gen eral purpose) output pin: the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 1: stsrxd_d_0_1: this output pin along with sts3 rxd_d_0[7:2] and sts3rxd_d_0_0 function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 0. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - encodis_0 (general purpose) output pin. this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 3 (encodis) within th e line interface drive register asso - ciated with channel 0 (indirect addr ess = 0x1e, 0x80), (direct address = 0x1f80). n ote : for product legacy purposes, this pin is called encodis_0 because one possible application is to tie this output pin to an encodis (b3zs/hdb3 encoder dis able) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and t he corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 101 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 e20 sts3rxd_d_0_2 ds3/e3/ sts1_data_out_ 0 rxsbdata_2 o cmos receive sts-3/stm-1 telecom bus - channel 0 - output data bus pin number 2/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 0 (ds3/e3/ sts1_data_out_0): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 2: stsrxd_d_0_2: this output pin along with sts3rx d_d_0[7:3] and sts3rxd_d_0[1:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 0. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3/ sts1_data_out line interface data output pin - channel 0: this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/sts-1 liu ic. this output pin should be c onnected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspondi ng to channel 0). by default, the data that is output via this output pin will be updated upon the rising edge of ds3/e3/sts1_clk_out_0 signal pin number c21. for ds3/e3 applications the xrt94l43 can be configured to update this output signal upon the falling edge of the ds3/e3/sts1_clk_0 signal by setting bit 2 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 0 (indirect address = 0x1e, 0x01), ( direct address = 0x1f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_0 signal upon the falling edge of ds3/e3/ sts1_clk_out_0. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 102 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper d20 sts3rxd_d_0_3 ds3/e3/ sts1_data_out_ 4 rxsbdata_3 o cmos receive sts-3/stm-1 telecom bus - channel 0 - output data bus pin number 3/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 4 (ds3/e3/ sts1_data_out_4): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 3: stsrxd_d_0_3: this output pin along with sts3rx d_d_0[7:4] and sts3rxd_d_0[2:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 0. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3/ sts1_data_out line interface data output pin - channel 4: this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/sts-1 liu ic. this output pin should be c onnected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspondi ng to channel 4). by default, the data that is output via this output pin will be updated upon the rising edge of the ds3/e3/sts1_clk_out_4 signal pin number e21. for ds3/e3 applications the xrt94l43 can be configured to update this output signal upon the falling edge of the ds3/e3/sts1_clk_4 signal by setting bit 2 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 4 (indirect address = 0x5e, 0x01), ( direct address = 0x5f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_4 signal upon the falling edge of ds3/e3/ sts1_clk_out_4. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 103 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 d21 sts3rxd_d_0_4 ds3/e3/ sts1_data_out_ 8 rxsbdata_4 o cmos receive sts-3/stm-1 telecom bus - channel 0 - output data bus pin number 4/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 8 (ds3/e3/ sts1_data_out_8): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 4: stsrxd_d_0_4: this output pin along with sts3rx d_d_0[7:5] and sts3rxd_d_0[3:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 0. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3/ sts1_data_out line interface data output pin - channel 8: this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/sts-1 liu ic. this output pin should be c onnected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspondi ng to channel 8). by default, the data that is being output via this ou tput pin will be updated upon the rising edge of the ds3/e3/sts-1_clk_out_8 signal pin number c24. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/sts1_data_8 output signal upon the falling edge of the ds3/e3/sts1_clk_8 signal by setting bit 2 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 8 (indirect addre ss = 0x9e, 0x01), (direct address = 0x9f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_8 signal upon the falling edge of ds3/e3/ sts1_clk_out_8. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 104 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper c21 sts3rxd_d_0_5 ds3/e3/ sts1_clk_out_0 rxsbdata_5 o cmos receive sts-3/stm-1 telecom bus - channel 0 - output data bus pin number 5/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 0: (ds3/e3/ sts1_clk_out_0): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 5: stsrxd_d_0_5: this output pin along with sts3rx d_d_0[7:6] and sts3rxd_d_0[4:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 0. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3/ sts1_clk_out line interface clock output pin - channel 0: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 0). by default, the data, which is being output via the ds3/e3/ sts1_data_out_0 output pin will be updated upon the rising edge of this clock output signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/sts1_data_0 output signal upon the falling edge of the ds3/e3/sts1_clk_0 signal by setting bit 0 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 0 (indirect addre ss = 0x1e, 0x01), (direct address = 0x1f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_0 signal upon the falling edge of ds3/e3/ sts1_clk_0. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 105 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 e21 sts3rxd_d_0_6 ds3/e3/ sts1_clk_out_4 rxsbdata_6 o cmos receive sts-3/stm-1 telecom bus - channel 0 - output data bus pin number 6/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 4: (ds3/e3/ sts1_clk_out_4): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 6: stsrxd_d_0_6: this output pin along with sts3rxd_d_0_7 and sts3rxd_d_0[5:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 0. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3/ sts1_clk_out line interface clock output pin - channel 4: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/e3/sts-1 liu ic. this output pin should be co nnected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 4). by default, the data, which is being output via the ds3/e3/ sts1_data_out_4 output pin will be updated upon the rising edge of this clock output signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/sts1_data_4 output signal upon the falling edge of the ds3/e3/sts1_clk_4 signal by setting bit 0 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 4 (indirect addre ss = 0x5e, 0x01), (direct address = 0x5f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_4 signal upon the falling edge of ds3/e3/ sts1_clk_4. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 106 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper c24 sts3rxd_d_0_7 ds3/e3/ sts1_clk_out_8 rxsbdata_7 o cmos receive sts-3/stm-1 telecom bus - channel 0 - output data bus pin number 7/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 8: (ds3/e3/ sts1_clk_out_8): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 7: stsrxd_d_0_7: this output pin along with sts3rxd_ d_0[6:0] function as the sts-3/ stm-1 receive (drop) telecom bus - output data bus for channel 0. the sts-3/stm-1 telecom bus interf ace will update the data via this output upon the rising edge of sts3rxd_clk_0. n ote : this output pin functions as the m sb (most significant bit) for the sts-3/stm-1 receive (drop) te lecom bus interface - output data bus (channel 0). if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3/ sts1_clk_out line interface clock output pin - channel 8: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 8). by default, the data, which is being output via the ds3/e3/ sts1_data_out_8 output pin will be updated upon the rising edge of this clock output signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/sts1_data_8 output signal upon the falling edge of the ds3/e3/sts1_clk_8 signal by setting bit 0 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 8 (indirect addre ss = 0x9e, 0x01), (direct address = 0x9f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_8 signal upon the falling edge of ds3/e3/ sts1_clk_8. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 107 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 e24 sts3rxd_d_1_0 txlev_1 rxsbdata_0 o cmos receive sts-3/stm-1 telecom bus - channel 1 - output data bus pin number 0/txlev_1 (general purpose) output pin: the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 0: stsrxd_d_1_0: this output pin along with sts3rxd_ d_1[7:1] function as the sts-3/ stm-1 receive (drop) telecom bus - output data bus for channel 1. the sts-3/stm-1 telecom bus interf ace will update the data via this output upon the rising edge of sts3rxd_clk_1. n ote : this input pin functions as the l sb (least significant bit) of the receive (drop) telecom bus for channel 1. if sts-3/stm-1 telecom bus (channel 1) is disabled - txlev_1 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 2 (txlev) within the line interface drive register associ - ated with channel 1 (indirect address = 0x2e, 0x80), (direct address = 0x2f80). n ote : for product legacy purposes, this pin is called txlev_1 because one possible application is to tie this output pin to a txlev (transmit line build-out disable) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. e23 sts3rxd_d_1_1 encodis_1 rxsbdata_1 o cmos receive sts-3/stm-1 telecom bus - channel 1 - output data bus pin number 1/encodis_1 (gen eral purpose) output pin: the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 1: stsrxd_d_1_1: this output pin along with sts3 rxd_d_1[7:2] and sts3rxd_d_1_0 function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 1. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_1. if sts-3/stm-1 telecom bus (chann el 1) is disabled - encodis_1 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 3 (encodis) within th e line interface drive register asso - ciated with channel 1 (indirect addr ess = 0x2e, 0x80), (direct address = 0x2f80). n ote : for product legacy purposes, this pin is called encodis_1 because one possible application is to tie this output pin to an encodis (b3zs/hdb3 encoder dis able) input pin from one of exar's xrt73l0x/xrt75l0x ds 3/e3/sts-1 liu devices. however, this output pin, and t he corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 108 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper f26 sts3rxd_d_1_2 ds3/e3/ sts1_data_out_ 1 rxsbdata_2 o cmos receive sts-3/stm-1 telecom bus - channel 1 - output data bus pin number 2/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 1 (ds3/e3/ sts1_data_out_1): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 2: stsrxd_d_1_2: this output pin along with sts3rx d_d_1[7:3] and sts3rxd_d_1[1:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 1. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_data_out line interface data output pin - channel 1: this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/sts-1 liu ic. this output pin should be c onnected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspondi ng to channel 1). by default, the data that is output via this output pin will be updated upon the rising edge of the ds3/e3/sts1_clk_out _1 signal pin number g26. for ds3/e3 applications the xrt94l43 can be configured to update this output signal upon the falling edge of the ds3/e3/sts1_clk_1 signal by setting bit 2 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 1 (indirect address = 0x2e, 0x01), ( direct address = 0x2f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_1 signal upon the falling edge of ds3/e3/ sts1_clk_out_1. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 109 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 h26 sts3rxd_d_1_3 ds3/e3/ sts1_data_out_ 5 rxsbdata_3 o cmos receive sts-3/stm-1 telecom bus - channel 1 - output data bus pin number 3/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 5 (ds3/e3/ sts1_data_out_5): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 3: stsrxd_d_1_3: this output pin along with sts3rx d_d_1[7:4] and sts3rxd_d_1[2:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 1. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_data_out line interface data output pin - channel 5. this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/sts-1 liu ic. this output pin should be c onnected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspondi ng to channel 5). by default, the data that is output via this output pin will be updated upon the rising edge of the ds3/e3/sts1_clk_out_5 signal pin number f25. for ds3/e3 applications the xrt94l43 can be configured to update this output signal upon the falling edge of the ds3/e3/sts1_clk_5 signal by setting bit 2 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 5 (indirect address = 0x6e, 0x01), ( direct address = 0x6f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_5 signal upon the falling edge of ds3/e3/ sts1_clk_out_5. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 110 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper j26 sts3rxd_d_1_4 ds3/e3/ sts1_data_out_ 9 rxsbdata_4 o cmos receive sts-3/stm-1 telecom bus - channel 1 - output data bus pin number 4/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 9 (ds3/e3/ sts1_data_out_9): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 4: stsrxd_d_1_4: this output pin along with sts3rx d_d_1[7:5] and sts3rxd_d_1[3:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 1. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_data_out line interface data output pin - channel 9. this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/sts-1 liu ic. this output pin should be c onnected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspondi ng to channel 9). by default, the data that is being output via this ou tput pin will be updated upon the rising edge of the ds3/e3/sts-1_clk_out_9 signal pin number h25. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/sts1_data_9 output signal upon the falling edge of the ds3/e3/sts1_clk_9 signal by setting bit 2 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 9 (indirect address = 0xae, 0x01), (direct address = 0xaf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_9 signal upon the falling edge of ds3/e3/ sts1_clk_out_9. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 111 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 g26 sts3rxd_d_1_5 ds3/e3/ sts1_clk_out_1 rxsbdata_5 o cmos receive sts-3/stm-1 telecom bus - channel 1 - output data bus pin number 5/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 1: (ds3/e3/ sts1_clk_out_1): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 5: stsrxd_d_1_5: this output pin along with sts3rx d_d_1[7:6] and sts3rxd_d_1[4:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 1. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_clk_out line interface clock output pin - channel 1: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/e3/sts-1 liu ic. this output pin should be co nnected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 1). by default, the data, which is being output via the ds3/e3/ sts1_data_out_1 output pin will be updated upon the rising edge of this clock output signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/sts1_data_1 output signal upon the falling edge of the ds3/e3/sts1_clk_1 signal by setting bit 0 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 1 (indirect addre ss = 0x2e, 0x01), (direct address = 0x2f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_1 signal upon the falling edge of ds3/e3/ sts1_clk_1. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 112 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper f25 sts3rxd_d_1_6 ds3/e3/ sts1_clk_out_5 rxsbdata_6 o cmos receive sts-3/stm-1 telecom bus - channel 1 - output data bus pin number 6/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 5: (ds3/e3/ sts1_clk_out_5): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 6: stsrxd_d_1_6: this output pin along with sts3rxd_d_1_7 and sts3rxd_d_1[5:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 1. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_clk_out line interface clock output pin - channel 5: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 5). by default, the data, which is being output via the ds3/e3/ sts1_data_out_5 output pin will be updated upon the rising edge of this clock output signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/sts1_data_5 output signal upon the falling edge of the ds3/e3/sts1_clk_5 signal by setting bit 0 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 5 (indirect addre ss = 0x6e, 0x01), (direct address = 0x6f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_5 signal upon the falling edge of ds3/e3/ sts1_clk_5. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 113 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 h25 sts3rxd_d_1_7 ds3/e3/ sts1_clk_out_9 rxsbdata_7 o cmos receive sts-3/stm-1 telecom bus - channel 1 - output data bus pin number 7/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 9: (ds3/e3/ sts1_clk_out_9): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 7: stsrxd_d_1_7: this output pin along with sts3rxd_ d_1[6:0] function as the sts-3/ stm-1 receive (drop) telecom bus - output data bus for channel 1. the sts-3/stm-1 telecom bus interf ace will update the data via this output upon the rising edge of sts3rxd_clk_1. n ote : this output pin functions as the m sb (most significant bit) for the sts-3/stm-1 receive (drop) te lecom bus interface - output data bus (channel 1). if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_clk_out line interface clock output pin - channel 9: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/e3/sts-1 liu ic. this output pin should be co nnected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 9). by default, the data, which is being output via the ds3/e3/ sts1_data_out_9 output pin will be updated upon the rising edge of this clock output pin. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/sts1_data_9 output signal upon the falling edge of the ds3/e3/sts1_clk_9 signal by setting bit 0 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 9 (indirect address = 0xae, 0x01), (direct address = 0xaf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_9 signal upon the falling edge of ds3/e3/ sts1_clk_9. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 114 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper y24 sts3rxd_d_2_0 txlev_2 rxsbdata_0 o cmos receive sts-3/stm-1 telecom bus - channel 2 - output data bus pin number 0/txlev_2 (general purpose) output pin: the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 0: stsrxd_d_2_0: this output pin along with sts3rxd_ d_2[7:1] function as the sts-3/ stm-1 receive (drop) telecom bus - output data bus for channel 2. the sts-3/stm-1 telecom bus interf ace will update the data via this output upon the rising edge of sts3rxd_clk_2. n ote : this input pin functions as the l sb (least significant bit) of the receive (drop) telecom bus for channel 2. if sts-3/stm-1 telecom bus (channel 2) is disabled - txlev_2 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 2 (txlev) within the line interface drive register associ - ated with channel 2 (indirect address = 0x3e, 0x80), (direct address = 0x3f80). n ote : for product legacy purposes, this pin is called txlev_2 because one possible application is to tie this output pin to a txlev (transmit line build-out disable) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. y23 sts3rxd_d_2_1 encodis_2 rxsbdata_1 o cmos receive sts-3/stm-1 telecom bus - channel 2 - output data bus pin number 1/encodis_2 (gen eral purpose) output pin: the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 1: stsrxd_d_2_1: this output pin along with sts3 rxd_d_2[7:2] and sts3rxd_d_2_0 function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 2. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - encodis_2 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 3 (encodis) within th e line interface drive register asso - ciated with channel 2 (indirect addr ess = 0x3e, 0x80), (direct address = 0x3f80). n ote : for product legacy purposes, this pin is called encodis_2 because one possible application is to tie this output pin to an encodis (b3zs/hdb3 encoder dis able) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and t he corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 115 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 w24 sts3rxd_d_2_2 ds3/e3/ sts1_data_out_ 2 rxsbdata_2 o cmos receive sts-3/stm-1 telecom bus - channel 2 - output data bus pin number 2/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 1 (ds3/e3/ sts1_data_out_2): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 2: stsrxd_d_2_2: this output pin along with sts3rx d_d_2[7:3] and sts3rxd_d_2[1:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 2. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_data_out line interface data output pin - channel 2. this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/sts-1 liu ic. this output pin should be c onnected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspondi ng to channel 2). by default, the data that is output via this output pin will be updated upon the rising edge of the ds3/e3/sts1_clk_out_2 signal pin number ac25. for ds3/e3 applications for ds3/e3 applications the xrt94l43 can be configured to update this output signal upon the falling edge of the ds3/e3/sts1_clk_2 signal by setting bit 2 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 2 (indirect addre ss = 0x3e, 0x01), (direct address = 0x3f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_2 signal upon the falling edge of ds3/e3/ sts1_clk_out_2. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 116 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ac24 sts3rxd_d_2_3 ds3/e3/ sts1_data_out_ 6 rxsbdata_3 o cmos receive sts-3/stm-1 telecom bus - channel 2 - output data bus pin number 3/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 6 (ds3/e3/ sts1_data_out_6): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 3: stsrxd_d_2_3: this output pin along with sts3rx d_d_2[7:4] and sts3rxd_d_2[2:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 2. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_data_out line interface data output pin - channel 6. this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/sts-1 liu ic. this output pin should be c onnected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspondi ng to channel 6). by default, the data that is output via this pin will be updated upon the rising edge of the ds3/e3/sts1_clk_out_6 signal pin number aa22. for ds3/e3 applications the xrt94l43 can be configured to update this output signal upon the falling edge of the ds3/e3/sts1_clk_6 signal by setting bit 2 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 6 (indirect address = 0x7e, 0x01), ( direct address = 0x7f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_6 signal upon the falling edge of ds3/e3/ sts1_clk_out_6. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 117 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ac21 sts3rxd_d_2_4 ds3/e3/ sts1_clk_out_10 rxsbdata_4 o cmos receive sts-3/stm-1 telecom bus - channel 2 - output data bus pin number 4/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 10 (ds3/e3/ sts1_data_out_10): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 4: stsrxd_d_2_4: this output pin along with sts3rx d_d_2[7:5] and sts3rxd_d_2[3:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 2. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_data_out line interface data output pin - channel 10. this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/sts-1 liu ic. this output pin should be c onnected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspondi ng to channel 10). by default, the data that is being output via the ds3/e3/sts1_data_out_10 output pin will be updated upon the rising edge of this output clock signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/sts1_data_10 output signal upon the falling edge of the ds3/e3/sts1_clk_10 signal by setting bit 2 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 10 (indirect address = 0xbe, 0x01), (direct address = 0xbf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_10 signal upon the falling edge of ds3/e3/ sts1_clk_out_10. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 118 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ac25 sts3rxd_d_2_5 ds3/e3/ sts1_clk_out_2 rxsbdata_5 o cmos receive sts-3/stm-1 telecom bus - channel 2 - output data bus pin number 5/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 2: (ds3/e3/ sts1_clk_out_2): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 5: stsrxd_d_2_5: this output pin along with sts3rx d_d_2[7:6] and sts3rxd_d_2[4:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 2. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_clk_out line interface clock output pin - channel 2: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 2). by default, the data, which is being output via the ds3/e3/ sts1_data_out_2 output pin will be updated upon the rising edge of this output clock signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/sts1_data_2 output signal upon the falling edge of the ds3/e3/sts1_clk_2 signal by setting bit 0 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 2 (indirect addre ss = 0x3e, 0x01), (direct address = 0x3f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_2 signal upon the falling edge of ds3/e3/ sts1_clk_2. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 119 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 aa22 sts3rxd_d_2_6 ds3/e3/ sts1_clk_out_6 rxsbdata_6 o cmos receive sts-3/stm-1 telecom bus - channel 2 - output data bus pin number 6/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 6: (ds3/e3/ sts1_clk_out_6): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 6: stsrxd_d_2_6: this output pin along with sts3rxd_d_2_7 and sts3rxd_d_2[5:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 2. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_clk_out line interface clock output pin - channel 6: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/e3/sts-1 liu ic. this output pin should be co nnected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 6). by default, the data, which is being output via the ds3/e3/ sts1_data_out_6 output pin will be updated upon the rising edge of this output clock signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/sts1_data_6 output signal upon the falling edge of the ds3/e3/sts1_clk_6 signal by setting bit 0 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 6 (indirect addre ss = 0x7e, 0x01), (direct address = 0x7f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_6 signal upon the falling edge of ds3/e3/ sts1_clk_6. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 120 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ae23 sts3rxd_d_2_7 ds3/e3/ sts1_clk_out_10 rxsbdata_7 o cmos receive sts-3/stm-1 telecom bus - channel 2 - output data bus pin number 7/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 10: (ds3/e3/ sts1_clk_out_10): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 7: stsrxd_d_2_7: this output pin along with sts3rxd_ d_2[6:0] function as the sts-3/ stm-1 receive (drop) telecom bus - output data bus for channel 2. the sts-3/stm-1 telecom bus interf ace will update the data via this output upon the rising edge of sts3rxd_clk_2. n ote : this output pin functions as the m sb (most significant bit) for the sts-3/stm-1 receive (drop) te lecom bus interface - output data bus (channel 2). if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_clk_out line interface clock output pin - channel 10: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 10). by default, the data, which is being output via the ds3/e3/ sts1_data_out_10 output pin will be updated upon the rising edge of this output clock signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/sts1_data_10 output signal upon the falling edge of the ds3/e3/sts1_clk_10 signal by setting bit 0 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 10 (indirect address = 0xbe, 0x01), (direct address = 0xbf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_10 signal upon the falling edge of ds3/e3/ sts1_clk_10. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 121 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ae21 sts3rxd_d_3_0 txlev_3 rxsbdata_0 o cmos receive sts-3/stm-1 telecom bus - channel 3 - output data bus pin number 0/txlev_3 (general purpose) output pin: the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 0: stsrxd_d_3_0: this output pin along with sts3rxd_ d_3[7:1] function as the sts-3/ stm-1 receive (drop) telecom bus - output data bus for channel 3. the sts-3/stm-1 telecom bus interf ace will update the data via this output upon the rising edge of sts3rxd_clk_3. n ote : this input pin functions as the l sb (least significant bit) of the receive (drop) telecom bus for channel 3. if sts-3/stm-1 telecom bus (channel 3) is disabled - txlev_3 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 2 (txlev) within the line interface drive register associ - ated with channel 3 (indirect address = 0x4e, 0x80), (direct address = 0x4f80). n ote : for product legacy purposes, this pin is called txlev_3 because one possible application is to tie this output pin to a txlev (transmit line build-out disable) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. ac19 sts3rxd_d_3_1 encodis_3 rxsbdata_1 o cmos receive sts-3/stm-1 telecom bus - channel 3 - output data bus pin number 1/encodis_3 (gen eral purpose) output pin: the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 1: stsrxd_d_3_1: this output pin along with sts3 rxd_d_3[7:2] and sts3rxd_d_3_0 function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 3. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_3. if sts-3/stm-1 telecom bus (chann el 3) is disabled - encodis_3 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 3 (encodis) within th e line interface drive register asso - ciated with channel 3 (indirect addr ess = 0x4e, 0x80), (direct address = 0x4f80). n ote : for product legacy purposes, this pin is called encodis_3 because one possible application is to tie this output pin to an encodis (b3zs/hdb3 encoder dis able) input pin from one of exar's xrt73l0x/xrt75l0x ds 3/e3/sts-1 liu devices. however, this output pin, and t he corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 122 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ab21 sts3rxd_d_3_2 ds3/e3/ sts1_data_out_ 3 rxsbdata_2 o cmos receive sts-3/stm-1 telecom bus - channel 3 - output data bus pin number 2/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 3 (ds3/e3/ sts1_data_out_3): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 2: stsrxd_d_3_2: this output pin along with sts3rx d_d_3[7:3] and sts3rxd_d_3[1:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 3. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_data_out line interface data output pin - channel 3. this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/sts-1 liu ic. this output pin should be c onnected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspondi ng to channel 3). by default, the data that is output via this pin will be updated upon the rising edge of the ds3/e3/sts1_clk_out_3 signal pin number ab20. for ds3/e3 applications the xrt94l43 can be configured to update this output signal upon the falling edge of the ds3/e3/sts1_clk_3 signal by setting bit 2 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 3 (indirect address = 0x4e, 0x01), ( direct address = 0x4f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_3 signal upon the falling edge of ds3/e3/ sts1_clk_out_3. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 123 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ae18 sts3rxd_d_3_3 ds3/e3/ sts1_data_out_ 7 rxsbdata_3 o cmos receive sts-3/stm-1 telecom bus - channel 3 - output data bus pin number 3/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 7 (ds3/e3/ sts1_data_out_7): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 3: stsrxd_d_3_3: this output pin along with sts3rx d_d_3[7:4] and sts3rxd_d_3[2:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 3. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_data_out line interface data output pin - channel 6. this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/sts-1 liu ic. this output pin should be c onnected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspondi ng to channel 7). by default, the data that is output via this pin will be updated upon the rising edge of the ds3/e3/sts1_clk_out_7 signal pin number ad19. for ds3/e3 applications the xrt94l43 can be configured to update this output signal upon the falling edge of the ds3/e3/sts1_clk_7 signal by setting bit 2 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 7 (indirect address = 0x8e, 0x01), ( direct address = 0x8f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_7 signal upon the falling edge of ds3/e3/ sts1_clk_out_7. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 124 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ae15 sts3rxd_d_3_4 ds3/e3/ sts1_data_out_ 11 rxsbdata_4 o cmos receive sts-3/stm-1 telecom bus - channel 3 - output data bus pin number 4/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 11 (ds3/e3/ sts1_data_out_11): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 4: stsrxd_d_3_4: this output pin along with sts3rx d_d_3[7:5] and sts3rxd_d_3[3:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 3. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_data_out line interface data output pin - channel 1. this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/sts-1 liu ic. this output pin should be c onnected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (corresponding to channel 11). by default, the data that is being output via this ou tput pin will be updated upon the rising edge of the ds3/e3/sts-1_clk_out_11 signal pin number ab15. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/sts1_data_11 output signal upon the falling edge of the ds3/e3/sts1_clk_11 signal by setting bit 2 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 11 (indirect address = 0xce, 0x01), (direct address = 0xcf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_11 signal upon the falling edge of ds3/e3/ sts1_clk_out_11. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 125 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ab20 sts3rxd_d_3_5 ds3/e3/ sts1_clk_out_3 rxsbdata_5 o cmos receive sts-3/stm-1 telecom bus - channel 3 - output data bus pin number 5/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 3: (ds3/e3/ sts1_clk_out_3): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 5: stsrxd_d_3_5: this output pin along with sts3rx d_d_3[7:6] and sts3rxd_d_3[4:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 3. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_clk_out line interface clock output pin - channel 3: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/e3/sts-1 liu ic. this output pin should be co nnected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 3). by default, the data, which is being output via the ds3/e3/ sts1_data_out_3 output pin will be updated upon the rising edge of this output pin. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/sts1_data_3 output signal upon the falling edge of the ds3/e3/sts1_clk_3 signal by setting bit 0 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 3 (indirect addre ss = 0x4e, 0x01), (direct address = 0x4f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_3 signal upon the falling edge of ds3/e3/ sts1_clk_3. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 126 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ad19 sts3rxd_d_3_6 ds3/e3/ sts1_clk_out_7 rxsbdata_6 o cmos receive sts-3/stm-1 telecom bus - channel 3 - output data bus pin number 6/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 7: (ds3/e3/ sts1_clk_out_7): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 6: stsrxd_d_3_6: this output pin along with sts3rxd_d_3_7 and sts3rxd_d_3[5:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 3. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_clk_out line interface clock output pin - channel 7: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 7). by default, the data, which is being output via the ds3/e3/ sts1_data_out_7 output pin will be updated upon the rising edge of this output pin. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/sts1_data_6 output signal upon the falling edge of the ds3/e3/sts1_clk_7 signal by setting bit 0 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 7 (indirect addre ss = 0x8e, 0x01), (direct address = 0x8f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_7 signal upon the falling edge of ds3/e3/ sts1_clk_7. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 127 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ab15 sts3rxd_d_3_7 ds3/e3/ sts1_clk_out_11 rxsbdata_7 o cmos receive sts-3/stm-1 telecom bus - channel 3 - output data bus pin number 7/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 11: (ds3/e3/ sts1_clk_out_11): the function of this output pin depends upon whether or not thests-3/ stm-1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/ stm-1 receive telecom bus - output data bus pin number 7: stsrxd_d_3_7: this output pin along with sts3rxd_ d_3[6:0] function as the sts-3/ stm-1 receive (drop) telecom bus - output data bus for channel 3. the sts-3/stm-1 telecom bus interf ace will update the data via this output upon the rising edge of sts3rxd_clk_3. n ote : this output pin functions as the m sb (most significant bit) for the sts-3/stm-1 receive (drop) te lecom bus interface - output data bus (channel 3). if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_clk_out line interface clock output pin - channel 11: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/e3/sts-1 liu ic. this output pin should be co nnected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 11). by default, the data, which is being output via the ds3/e3/ sts1_data_out_11 output pin will be updated upon the rising edge of this clock output signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/sts1_data_11 output signal upon the falling edge of the ds3/e3/sts1_clk_11 signal by setting bit 0 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 11 (indirect address = 0xce, 0x01), (direct address = 0xcf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_11 signal upon the falling edge of ds3/e3/ sts1_clk_11. sts-3/stm-1 telecom bus inte rface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 128 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper receive transport overhead interface p in # s ignal n ame i/o s ignal t ype d escription y5 rxtohclk o cmos receive toh output port - clock output: this output pin, along with rxtoh, rxtohvalid and rxtohframe func - tion as the receive toh output port: the receive toh output port is us ed to obtain the value of the toh bytes, within the incoming sts-12/stm-4 signal. this output pin provides a clock signal. if the rxtohvalid output pin is "high" , then the contents of the toh bytes within the incoming sts-12 data-stream, will be serially output via the rxtoh output. this data will be updated upon the falling edge of this clock signal. therefore, it is advisable to sample the data (at the rxtoh output pin) upon the rising edge of this clock output signal. w5 rxtohvalid o cmos receive toh output port - toh valid (or ready) indicator: this output pin, along with rxtoh and rxtohframe function as the receive toh output port. this output pin will toggle "high" whenev er valid toh data is being output via the rxtoh output pin. v6 rxtoh o cmos receive toh output port - output pin: this output pin, along with rxtohclk, rxtohvalid and rxtohframe function as the receive toh output port. all toh data, that resides within the incoming sts-12 data-stream will be output via this output pin. the rxtohvalid output pin will toggle "high", coincident with anytime a bit (from the receive sts-12 toh data) is being output via this output pin. the rxtohframe output pin will pulse "high" (for eight periods of rxto - hclk) coincident to when the a1 byte is being output via this output pin. data, on this output pin, is updated upon the falling edge of rxtohclk. w6 rxtohframe o cmos receive toh output port - sts-12/stm-4 frame indicator: this output pin, along with the rxtohc lk, rxtohvalid and rxtoh output pins function as the receive toh output port. this output pin will pulse "high", for one period of rxtohclk, one rxto - hclk period prior to the very first toh bit (of a given sts-12 frame) being output via the rxtoh output pin. w2 rxldccval o cmos receive - line dcc output port - dcc value indicator output pin: this output pin, along with the rxto hclk and the rxldcc output pins function as the receive line dcc output port of the xrt94l43. this output pin pulses "high" coincident to when the receive line dcc output port outputs a dcc bit via the rxldcc output pin. this output pin is updated u pon the falling edge of rxtohclk. the line dcc hdlc controller circuitry th at is interfaced to this output pin, the rxldcc and the rxtohclk pins is suppose to do the following. 1. it should continuously sample and monitor the state of this output pin upon the rising edge of rxtohclk. 2. anytime the line dcc hdlc circuitry samples this output pin being "high", it should sample and latch the data on the rxldcc output pin (as a valid line dcc bit) into the line dcc hdlc circuitry.
xrt94l43 129 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 w3 rxldcc o cmos receive - line dcc output port - output pin: this output pin, along with rxldccv al and the rxtohclk output pins function as the receive line dcc output port of the xrt94l43. this pin outputs the contents of the line dcc (e.g., the d4, d5, d6, d7, d8, d9, d10, d11 and d12 bytes), within the incoming sts-12 data- stream. the receive line dcc output port will assert the rxldccval output pin, in order to indicate that the data, residing on the rxldcc out - put pin is a valid line dcc byte. the receive line dcc output port will update the rxldccval and the rxldcc output pins upon the falling edge of the rxtohclk output pin. t he line dcc hdlc circuitry that is interfaced to this output pin, the rxldccval and the rxtohclk pins is suppose to do the following. 1. it should continuously sample and monitor the state of the rxldccval output pin upon the rising edge of rxtohclk. 2. anytime the line dcc hdlc circuitry samples the rxldccval output pin "high", it should sample and latch the contents of this output pin (as a valid line dcc bit) into the line dcc hdlc circuitry. y1 rxe1f1e2fp o cmos receive - order-wire output port - frame boundary indicator: this output pin, along with rxe1f1e2, rxe1f1e2val and the rxtohclk output pins function as the rece ive order-wire output port of the xrt94l43. this output pin pulses "high" (for one period of rxtohclk) coincident to when the very first bit (of the e1 byte) is being output via the rxe1f1e2 output pin. y2 rxe1f1e2 o cmos receive - order-wire output port - output pin: this output pin, along with rxe1f1e2val, rxe1f1f2fp, and the rxto - hclk output pins function as the re ceive order-wire output port of the xrt94l43. this pin outputs the contents of the order-wire bytes (e.g., the e1, f1 and e2 bytes) within the incoming sts-12 data-stream. the receive order-wire output port will pulse the rxe1f1e2fp output pin "high" (for one period of rxtohclk) coincident to when the very first bit (of the e1 byte) is being output via the rxe1f1e2 output pin. addition - ally, the receive order-wire output port will also assert the rxe1f1e2val output pin, in order to indicate that the data, residing on the rxe1f1e2 output pin is a valid order-wire byte. the receive order-wire output port will update the rxe1f1e2val, the rxe1f1e2fp and the rxe1f1e2 output pins upon the falling edge of the rxtohclk output pin. the receive order-wire circuitry that is interfaced to this output pin, and the rxe1f1e2val, the rxe1f1e2 and the rxtohclk pins is suppose to do the following; 1. it should continuously samp le and monitor the state of the rxe1f1e2val and rxe1f1e2fp output pins upon the rising edge of rxtohclk. 2. anytime the order-wire circui try samples the rxe1f1e2val and rxe1f1e2fp output pins "high", it should begin to sample and latch the contents of this output pin (as a valid order-wire bit) into the order-wire circuitry. 3. the order-wire circuitry should continue to sample and latch the con - tents of the output pin until the rxe1 f2e2val output pin is sampled "low". receive transport overhead interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 130 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ab5 rxsdcc o cmos receive - section dcc output port - output pin: this output pin, along with rxsdcc val and the rxtohclk output pins function as the receive section dcc output port of the xrt94l43. this pin outputs the content s of the section dcc (e.g., the d1, d2 and d3 bytes), within the incoming sts-12 data-stream. the receive section dcc output port will assert the rxsdccv al output pin, in order to indi - cate that the data, residing on the rxsdcc output pin is a valid section dcc byte. the receive section d cc output port will update the rxsdc - cval and the rxsdcc output pins up on the falling edge of the rxtohclk output pin. the section dcc hdlc circuitry that is interfaced to this output pin, the rxsdccval and the rxtohclk pins is suppose to do the follow - ing. 1. it should continuously sample and monitor the state of the rxsdccval output pin upon the rising edge of rxtohclk. 2. anytime the section dcc hdlc ci rcuitry samples the rxsdccval out - put pin "high", it should sample and latch the contents of this output pin (as a valid section dcc bit) into the section dcc hdlc circuitry. aa5 rxsdccval o cmos receive - section dcc output port - dcc value indicator output pin: this output pin, along with the rx tohclk and the rxsdcc output pins function as the receive section dcc output port of the xrt94l43. this output pin pulses "high" coincident to when the receive section dcc output port outputs a dcc bit via the rxsdcc output pin. this output pin is updated u pon the falling edge of rxtohclk. the section dcc hdlc controller circuitry that is interfaced to this output pin, the rxsdcc and the rxtohclk pins is suppose to do the following. 1. it should continuously sample and monitor the state of this output pin upon the rising edge of rxtohclk. 2. anytime the section dcc hdlc circuitry samples this output pin being "high", it should sample and latch the data on the rxsdcc output pin (as a valid section dcc bit) into the section dcc hdlc circuitry. w4 rxe1f1e2val o cmos receive - order wire output port - e1f1e2 value indicator output pin: this output pin, along with the rxtohclk, rxe1f1e2fp, rxe1f1e2 and rxtohclk output pins function as the receive - order wire output port of the xrt94l43. this output pin pulses "high" coincident to when the receive - order wire output port outputs the contents of an e1, f1 or e2 byte, via the rxe1f1e2 output pin. this output pin is updated u pon the falling edge of rxtohclk. the receive order-wire circuitry, that is interfaced to this output pin, the rxe1f1e2 and the rxtohclk pins is suppose to do the following. 1. it should continuously sample and monitor the state of this output pin upon the rising edge of rxtohclk. 2. anytime the receive order-wire circuitry samples this output pin being "high", it should sample and latch the data on the rxe1f1e2 output pin (as a valid order-wire bit) into the receive order-wire circuitry. receive transport overhead interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 131 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 b8 b4 aa3 ae3 c6 a1 ab3 ae4 c5 b7 ac3 af3 a8 a3 y3 ad3 rxpoh_0 rxpoh_1 rxpoh_2 rxpoh_3 rxpoh_4 rxpoh_5 rxpoh_6 rxpoh_7 rxpoh_8 rxpoh_9 rxpoh_10 rxpoh_11 rxpoh_12 rxpoh_13 rxpoh_14 rxpoh_15 o cmos receive sonet poh processor block - path overhead output port - output pin: these output pins, along with the rxpohclk_n, rxpohframe_n and rxpohvalid_n function as the receive sonet poh processor block - poh output port. these pins serially output the poh data that have been received by each of the receive sonet poh processor blocks (via the incoming sts-12 data-stream). each bit, within the po h bytes is updated (via these output pins) upon the falling edge of rxpohclk_n. as a consequence, external circuitry receiving this data, should sample this data upon the rising edge of rxpohclk_n. b9 b5 aa4 aa8 b6 c4 ab4 ae5 e7 a5 ac4 ab8 a9 d6 y4 ad4 rxpohclk_0 rxpohclk_1 rxpohclk_2 rxpohclk_3 rxpohclk_4 rxpohclk_5 rxpohclk_6 rxpohclk_7 rxpohclk_8 rxpohclk_9 rxpohclk_10 rxpohclk_11 rxpohclk_12 rxpohclk_13 rxpohclk_14 rxpohclk_15 o cmos receive sonet poh processor block - path overhead output port - clock output signal: these output pins, along with rxpoh_n, rxpohframe_n and rxpohvalid_n function as the receive sonet poh processor block - poh output port. these output pins function as the clock output signals for the receive sonet poh processor block - po h output port. the rxpoh_n, rxpohframe_n and rxpohvalid_n ou tput pins are updated upon the falling edge of this clock signal. as a consequence, the external circuitry should sample these signals upon the rising edge of this clock signal. receive transport overhead interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 132 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper b3 c3 ab1 af1 d4 f7 ac1 ac5 f5 c7 ad1 ad5 f8 e4 aa1 ae1 rxpohframe_0 rxpohframe_1 rxpohframe_2 rxpohframe_3 rxpohframe_4 rxpohframe_5 rxpohframe_6 rxpohframe_7 rxpohframe_8 rxpohframe_9 rxpohframe_10 rxpohframe_11 rxpohframe_12 rxpohframe_13 rxpohframe_14 rxpohframe_15 o cmos receive sonet poh processor block - path overhead output port - frame boundary indicator: these output pins, along with the rxpoh_n, rxpohclk_n and rxpohvalid_n output pins function as the receive sonet poh proces - sor block - path overhead output port. these output pins will pulse "high" co incident with the very first poh byte (j1), of a given sts-1 frame, is being output via the corresponding rxpoh_n output pin. receive transport overhead interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 133 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 e6 d3 ab2 af2 d5 a4 ac2 ac6 a2 c9 ad2 ac7 c8 e5 aa2 ae2 rxpohvalid_0 rxpohvalid_1 rxpohvalid_2 rxpohvalid_3 rxpohvalid_4 rxpohvalid_5 rxpohvalid_6 rxpohvalid_7 rxpohvalid_8 rxpohvalid_9 rxpohvalid_10 rxpohvalid_11 rxpohvalid_12 rxpohvalid_13 rxpohvalid_14 rxpohvalid_15 o cmos receive sonet poh processor block - path overhead output port - valid poh data indicator: these output pins, along with rxpoh_n, rxpohclk_n and rxpohframe_n function as the rece ive sonet poh processor block - path overhead output port. these output pins will toggle "high" coincident with when valid poh data is being output via the rxpoh_n output pins. this output is updated upon the falling edge of rxpohclk_n. hence, external circuitry should sample these signals upon rising edge of rxpohclk_n. aa7 lof 8khz_out o cmos receive sts-12 lof (loss of frame) indicator/8khz clock output: the function of this output pin de pends upon whether or not the 8khz clock generation feature has been enabled. 8khz clock generation feature - not enabled (nor mal mode) - the sts-12 loss of frame indicator output: this output pin indicates whether or not the receive sts-12 toh proces - sor block (within the device) is declaring the lof condition. "low" - indicates that the receive sts-12 toh processor block is not currently declaring the lof condition. "high" - indicates that the receive sts-12 toh processor block is cur - rently declaring the lof condition. 8khz clock generation feature - enabled - 8khz clock output: if this feature is enabled, the xrt94l 43 will be configured to derive and generate 8khz clock output signals, from a particular sts-1 signal that is being received via one of the 12 receive sts-1 toh/poh processor blocks. receive transport overhead interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 134 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper
xrt94l43 135 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 general purpose input/output p in # s ignal n ame i/o s ignal t ype d escription a19 gpio_0 extlos_0 sse_clk i/o ttl/ cmos general purpose input/output pin or external los input pin/slow- speed interface - egress - clock i/o: the function of this input pin depend s on whether or not channel 0 of the ds3/e3 framer block is enabled or whether or not the slow-speed interface is enabled. gpio_0 (ds3/e3 framer block - channel 0 is disabled). if the ds3/e3 framer block is disabl ed, then this pin will function as a general purpose input/output pin. this input pin can be configured to f unction as either an input or output pin by writing the appropriate value into bit 0 (gpio_dir_0), within the operation general purpos e input/output direction re gister - 0 (indirect address = 0x00, 0x4b), (direct address = 0x014b). when configured as an input pin, the state of this pin can be monitored by reading the state of bit 0 (gpio _0) within the oper ation general pur - pose input/output regist er - byte 0 (indirect address = 0x00, 047), (direct address = 0x0147). when configured as an output pin, the state of this pin can be controlled by writing the appropriate value into bit 0 (gpio_0) within the operation general purpose input/output regist er - byte 0 (indirect address = 0x00, 0x47), (direct address = 0x047). extlos_0 (ds3/e3 framer block - channel 0 is enabled). if the ds3/e3 framer block is enabl ed, then this pin will function as the external los input pin for channel 0. this input pin is intended to be connected to a los output pin of a ds3/e3 liu ic. if this input pin is pulled "high", then the corresponding ds3/e3 framer block will automatically declare an los condition. sse_clk (slow-speed interface - egress port is enabled): if the slow-speed interface - egress (sse) port is enabled, then this pin will function as either the sse_cl k output pin or the sse_clk input pin. if the user configures the sse port to operate in the "insert" mode, then the sse port will be configured to replace any "user-selected" egress ds3/e3 or sts-1 data-stream (within the xrt94l43) with the data that is applied to the sse_pos and sse_neg input pins. more specifically, in the insert mode, this pin will function as the sse_clk input pin. in this case, the sse port will sample and latch the contents of the sse_pos and sse_neg input pins upon the falling edge of this input clock signal. if the user configures the sse port to operate in the "e xtract" mode, then the sse port will output any "user-selected" egress ds3/e3 or sts-1 signal (within the xrt94l43) via this output port. more specifically, in the "extract mode", this pin will function as the sse_clk output pin. in this case, the sse port will output the data (via the sse_pos and sse_neg output pins) upon the rising edge of this output clock signal.
xrt94l43 136 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper d22 gpio_1 extlos_1 ssi_clk i/o ttl/ cmos general purpose input/output pin or external los input pin/slow- speed interface - ingress - clock i/o: the function of this input pin depend s on whether or not channel 1 of the ds3/e3 framer block is enabled, or whether or not the slow speed interface is enabled. gpio_1 (ds3/e3 framer block - channel 1 is disabled). if the ds3/e3 framer block is disabl ed, then this pin will function as a general purpose input/output pin. this input pin can be configured to f unction as either an input or output pin by writing the appropriate value into bit 1 (gpio_dir_1), within the operation general purpos e input/output direction register - 0 (indirect address = 0x00, 0x4b), (direct address = 0x014b). when configured as an input pin, the state of this pin can be monitored by reading the state of bit 1 (gpio _1) within the oper ation general pur - pose input/output regist er - byte 0 (indirect address = 0x00, 047). when configured as an output pin, the state of this pin can be controlled by writing the appropriate value into bit 1 (gpio_1) within the operation general purpose input/output regist er - byte 0 (indirect address = 0x00, 0x47), (direct address = 0x0147). extlos_1 (ds3/e3 framer block - channel 1 is enabled), slow- speed interface is disabled). if the ds3/e3 framer block is enabl ed, then this pin will function as the external los input pin for channel 1. this input pin is intended to be connected to an los output pin of a ds3/e3 liu ic. if this input pin is pulled "high", then the corresponding ds3/e3 framer block will automatically declare an los condition. ssi_clk (slow-speed interface - ingress port is enabled): if the slow-speed interface -ingress (s si) port is enabled, then this pin will function as either the ssi_clk output pin or the ssi_clk input pin. if the user configures t he ssi port to operate in the "insert" mode, then the ssi port will be configured to replace any "user-selected" ingress ds3/e3 or sts-1 data-stream (within the xrt94l43) with the data that is applied to the ssi_pos and ssi_neg input pins. more specifically, in the "insert" mode, this pin will functi on as the "ssi_clk" input pin. in this case, the ssi port will sample and latch the contents of the ssi_pos and ssi_neg input pins upon the falling edge of this input clock signal. if the user configures the ssi port to operate in the "extract" mode, then the ssi port will output any "user-selected" ingress ds3/e3 or sts-1 signal (within the xrt94l43) via this output port. more specifically, in the "extract mode", this pin will functi on as the ssi_clk output pin. in this case, the ssi port will output the data (via the ssi_pos and ssi_neg output pins) upon the rising edge of this output clock signal. general purpose input/output p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 137 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 w25 gpio_2 extlos_2 ssi_pos i/o ttl/ cmos general purpose input/output pin or external los input pin/slow- speed interface -ingress - positive data i/o: the function of this input pin depend s on whether or not channel 2 of the ds3/e3 framer block is enabled.. gpio_2 (ds3/e3 framer block - channel 2 is disabled). if the ds3/e3 framer block is disabl ed, then this pin will function as a general purpose input/output pin. th is input pin can be configured to function as either an input or output pin by writing the appropriate value into bit 2 (gpio_dir_2), within t he operation general purpose input/ output direction register - 0 (indirect address = 0x00, 0x4b), (direct address = 0x014b). when configured as an input pin, the state of this pin can be monitored by reading the state of bit 2 (gpio _2) within the oper ation general pur - pose input/output regist er - byte 0 (indirect address = 0x00, 047), (direct address = 0x0147). when configured as an output pin, the state of this pin can be controlled by writing the appropriate value into bit 2 (gpio_2) within the operation general purpose input/output regist er - byte 0 (indirect address = 0x00, 0x47), (direct address = 0x0147). extlos_2 (ds3/e3 framer block - channel 2 is enabled, slow- speed interface is disabled). if the ds3/e3 framer block is enabl ed, then this pin will function as the external los input pin for channel 2. this input pin is intended to be connected to an los output pin of a ds3/e3 liu ic. if this input pin is pulled "high", then the corresponding ds3/e3 framer block will automatically declare an los condition. ssi_pos (slow-speed interface - ingress port is enabled): if the slow-speed interface - ingress ( ssi) port is enabled, then this pin will function as either the ssi_pos output pin or the ssi_pos input pin. if the user configures t he ssi port to operate in the "insert" mode, then the ssi port will be configured to replace any "user-selected" ingress ds3/e3 or sts-1 data-stream (within the xrt94l43) with the data that is applied to the ssi_pos and ssi_neg input pins. more specifically, in the "insert" mode, this pin will function as the ssi_pos input pin. in this case, the ssi port will sample and latch the contents of this input pin (along with ssi_neg, in a dual-rail manner) upon the falling edge of the ssi_clk input clock signal. if the user configures the ssi port to operate in the "extract" mode, then the ssi port will output any "user-selected" ingress ds3/e3 or sts-1 signal (within the xrt94l43) via this output port. more specifically, in the "extract mode", this pin will functi on as the ssi_pos output pin. in this case, the ssi port will output data via this pin, along with the ssi_neg output pin (in a dual-rail manner) upon the rising edge of the ssi_clk output signal. general purpose input/output p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 138 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ac22 gpio_3 extlos_3 sse_neg i/o ttl/ cmos general purpose input/output pin or external los input pin/slow- speed interface - egress - negative data i/o: the function of this input pin depend s on whether or not channel 3 of the ds3/e3 framer block is enabled, or wheter or not the slow speed interface is enabled. gpio_3 (ds3/e3 framer block - channel 3 is disabled). if the ds3/e3 framer block is disabl ed, then this pin will function as a general purpose input/output pin. this input pin can be configured to f unction as either an input or output pin by writing the appropriate value into bit 3 (gpio_dir_3), within the operation general purpos e input/output direction register - 0 (indirect address = 0x00, 0x4b), (direct address = 0x014b). when configured as an input pin, the state of this pin can be monitored by reading the state of bit 3 (gpio _3) within the oper ation general pur - pose input/output regist er - byte 0 (indirect address = 0x00, 047), (direct address = 0x0147). when configured as an output pin, the state of this pin can be controlled by writing the appropriate value into bit 3 (gpio_3) within the operation general purpose input/output regist er - byte 0 (indirect address = 0x00, 0x47), (direct address = 0x0147). extlos_3 (ds3/e3 framer block - channel 3 is enabled, slow- speed interface is disabled). if the ds3/e3 framer block is enabl ed, then this pin will function as the external los input pin for channel 3. this input pin is intended to be connected to an los output pin of a ds3/e3 liu ic. if this input pin is pulled "high", then the corresponding ds3/e3 framer block will automatically declare an los condition. sse_neg (slow-speed interface - egress port is enabled): if the slow-speed interface - egress (sse) port is enabled, then this pin will function as either the sse_ neg output pin or the sse_neg input pin. if the user configures the sse port to operate in the "insert" mode, then the sse port will be configured to replace any "user-selected" egress ds3/e3 or sts-1 data-stream (within the xrt94l43) with the data that is applied to the sse_pos and sse_neg input pins. more specifically, in the "insert" mode, this pin will func tion as the sse_neg input pin. in this case, the sse port will sample an d latch the content s of this input pin (along with sse_pos, in a dual-rail manner) upon the falling edge of the sse_clk in put clock signal. if the user configures the sse port to operate in the "e xtract" mode, then the sse port will output any "user-selected" egress ds3/e3 or sts-1 signal (within the xrt94l43) via this output port. more specifically, in the "extract mode" this pin will function as the sse_neg output pin. in this case, the sse port will output data via this pin, along with the sse_pos output pin (in a dual-rail manner) upon the rising edge of the sse_clk output signal general purpose input/output p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 139 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 clock inputs p in # s ignal n ame i/o s ignal t ype d escription p23 refclk34 i ttl e3 reference clock inpu t for the jitter attenuat or within the ds3/e3 mapper block: apply a signal with a frequency of 34.36820ppm to this input pin. this input pin functions as the timing reference for the ds3/e3/sts-1 jitter attenuator (within the ds3/e3 mapper block) for e3 applications. p24 refclk51 i ttl sts-1 reference clock input for the jitter attenuator within the ds3/ e3 mapper block: the user is expected to apply a signal with a frequency of 51.84mhz20ppm to this input pin. th is input pin functions as the timing reference for the ds3/e3/sts-1 jitte r attenuator (within the ds3/e3 map - per block) for sts-1 applications. p25 refclk45 i ttl ds3 reference clock input for the jitt er attenuator wi thin the ds3/e3 mapper block: apply a signal with a frequency of 44.73620ppm to this input pin. this input pin functions as the timing reference for the ds3/e3/sts-1 jitter attenuator (within the ds3/e3 map per block) for ds3 applications. boundary scan p in # s ignal n ame i/o s ignal t ype d escription b2 tdo o c2 tdi i b1 trst i g5 tck i h6 tms i miscellaneous pins p in # s ignal n ame i/o s ignal t ype d escription l21 te s t m o d e i test mode input pin: tie this input pin "low" for normal operation.
xrt94l43 140 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper power supply pins p in # s ignal n ame i/o s ignal t ype d escription vdd = 3.3v n6 n5 p3 r3 analog vdd pins (transmitter) _ transmitter analog power supply voltage = 3.3v nominal p4 analog vdd pins (pll) pll analog power supply voltage = 3.3v nominal l1 analog vdd pins (receiver) receiver analog power supply voltage = 3.3v nominal u6 r15 r16 p15 p16 n15 n16 m15 m16 l15 l16 aa10 aa11 aa9 f10 f11 f9 k21 digital vdd digital power supply voltage = 3.3v nominal vdd (2.5v) p6 m4 n21 n26 p22 analog vdd pins (pll) pll analog power supply voltage = 2.5 v nominal r6 analog vdd pins (transmitter) transmitter analog power supply voltage = 2.5 v nominal
xrt94l43 141 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 l6 analog vdd pins (receiver) receiver analog power supply voltage = 2.5 v nominal u21 r11 r12 p11 p12 n11 n12 m11 m12 l11 l12 k6 f16 f17 f18 aa16 aa17 aa18 digital vdd digital power supply voltage = 2.5 v nominal power supply pins p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 142 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ground p in # s ignal n ame i/o s ignal t ype d escription y6 y21 t11 t12 t13 t14 t15 t16 r13 r14 p13 p14 n13 n14 m13 m14 l13 l14 g6 g21 f6 f21 f13 f14 aa6 aa21 aa13 aa14 gnd _ ground n3 n4 m3 r5 p5 t6 l2 m6 m21 n24 n25 n22 n23 p21 analog ground no connects m23 nc
xrt94l43 143 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 m26 nc t5 nc ground p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 144 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper pin descriptions - indirect addressing microprocessor interface p in # s ignal n ame i/o s ignal t ype d escription u22 pclk i ttl microprocessor interface clock input: this clock input signal is used for synchronous/burst/dma data transfer operations. this clock can be running up to 66mhz. l25 l23 l22 ptype_0 ptype_1 ptype_2 i ttl microprocessor type select input: these three input pins are used to configure the microprocessor interface block to readily support a wide variety of microprocessor interfaces. the relationship between the settings of these input pins and the corresponding microprocessor interface configuration is presented below. ptype[2:0] microprocessor interface mode 000 asynchronous intel l001 asynchronous motorola 010 intel x86 011 intel i960, motorola mpc860 100 idt3051/52 (mips) 101 ibm power pc v26 r24 p26 m24 t26 m22 m25 l26 paddr_0 paddr_1 paddr_2 paddr_3 paddr_4 paddr_5 paddr_6 paddr_7 i ttl address bus input pins (microprocessor interface): these pins are used to select the on-chip mapper/framer registers and ram space for read and write operations with the microprocessor. t22 r22 u24 r21 w26 t25 r25 r26 pdata_0 pdata_1 pdata_2 pdata_3 pdata_4 pdata_5 pdata_6 pdata_7 i/o ttl bi-directional data bus pins (microprocessor interface): these pins are used to drive and rece ive data over the bi-directional data bus. y26 pwr_l i ttl write strobe (intel mode): if the microprocessor interface is configured to operate in the intel mode, then this active-low input pin functions as the wr (write strobe) input sig - nal from the microprocessor. once this active-low signal is asserted, the mapper/framer will latch the contents of the bi-directional data (d[7:0]) into the addressed registers (or buffer location) within the mapper/framer. r/w input pin (motorola mode): when the microprocessor interface section is operating in the motorola mode, then this pin is functionally equivalent to the r/w pin. in the motorola mode, a read operation occurs if this pin is at a logic 1. similarly a write operation occurs if this pin is at a logic 0.
xrt94l43 145 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 t23 prd_l i ttl read strobe (intel mode): if the microprocessor interface is operating in the intel mode, then this input pin will function as the rd* (read strobe) input signal from the micropro - cessor. once this active-low signal is asserted, then the mapper/framer will place the contents of the addressed re gister (within the mapper/framer ic) on the microprocessor bi-directional data bus (d[7:0]). when this signal is negated, the data bus will be tri-stated. data strobe (mo torola mode). if the microprocessor interface is operat ing in the motorola mode, then this input will function as the ds* (data strobe) signal. r23 pas_l i ttl address latch enable/address strobe: this input pin is used to latch the address (present at the microprocessor interface address bus pins (a[6:0]) into the mapper/framer microprocessor interface block and to i ndicate the start of a re ad or write cycle. this input pin is active-high, in the intel mode and active-low in the motorola mode. v22 pcs_l i ttl chip select input: this active "low" signal must be asserted in order to select the micropro - cessor interface for read and write operations between the micropro - cessor and the mapper/framer on-chip registers and ram locations. y25 prdy_l o cmos ready or dtack: this active-low output pin will func tion as the ready output when the microprocessor interface is configured to operate in the intel mode; and will function as the dtack output, when the microprocessor interface is run - ning in the motorola mode. intel mode - ready output: when the mapper/framer negates this out put pin (e.g., toggles it "low") it indicates (to the microprocessor) that the current read or write opera - tion is to be extended until this signal is asserted (e.g., toggled "high"). motorola mode - dtack (data transfer acknowledge) output: the mapper/framer will assert this pin in order to inform the microproces - sor that the present read or write cy cle is nearly complete. if the map - per/framer requires that the current read or write cycle be extended, then the mapper/framer will delay its assertion of this signal. the 68000 family of microprocessors require this signal from its peripheral devices, in order to quickly and properly complete a read or write cycle. t21 pdben_l i ttl bi-directional data bus enable input pin: if the microprocessor interface is operati ng in the intel-i960 mode, then this input pin is used to enable the bi-directional data bus. setting this input pin "low" enables the bi-directional data bus. setting this input "high" tri-states the bi-directional data bus. microprocessor interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 146 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper u25 pblast_l i ttl last burst transfer indicator input pin: if the microprocessor interface is operati ng in the intel-i960 mode, then this input pin is used to indicate (to the microprocessor interfac e block) that the current data transfer is the last data transfer within the current burst opera - tion. the microprocessor should assert this input pin (by toggling it "low") in order to denote that the current r ead or write operation (within a burst operation) is the last oper ation of this burst operation. ac26 pint_l o cmos interrupt request output: this open-drain, active-low output signal will be asserted when the mapper/ framer device is requesting interrupt se rvice from the microprocessor. this output pin should typically be connect ed to the interrupt request input of the microprocessor. l24 reset_l i ttl reset input: when this active-low signal is asserted, the xrt94l43 will be asynchro - nously reset. when this occurs, all out puts will be tri-stated and all on-chip registers will be reset to their default values. sonet/sdh serial line interface pins p in # s ignal n ame i/o s ignal t ype d escription m5 rxl_clkl_p i lvpecl receive sts-12/stm-4 clock - positive polarity pecl input: this input pin, along with rxl_clkl_n functions as the recov - ered clock input, from a system back-plane or an optical trans - ceiver. the receive sts-12/stm-4 interface block will sample the data, applied at the rxldata_p/rxldata_n input pins, upon the rising edge of this signal. n ote : for aps (automatic protection switching) purposes, this input pin, along with rxl_clkl_n functions as the primary receive clock input port. l5 rxl_clkl_n i lvpecl receive sts-12/stm-4 clock - ne gative polarity pecl input: this input pin, along with rxl_clkl_p functions as the recov - ered clock input, from a system back-plane or an optical trans - ceiver. the receiver sts-12/stm-4 interface block will sample the data applied at the rxldata_p/rxldata_n input pins, upon the falling edge of this signal. n ote : for aps (automatic protection switching) purposes, this input pin, along with rxl_ clkl_p functions as the primary receive clock input port. microprocessor interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 147 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 k2 rxl_clkl_r_p i lvpecl receive sts-12/stm-4 clock - po sitive polarity pecl input - redundant port: this input pin, along with rxl_clkl_r_n functions as the recov - ered clock input, from a system back-plane or an optical trans - ceiver. the receive sts-12/stm-4 interface block will sample the data, applied at the rxldata_p/rxldata_n input pins, upon the rising edge of this signal. n ote : for aps (automatic protection switching) purposes, this input pin, along with rxl_c lkl_r_n functions as the redundant receive clock input port. k1 rxl_clkl_r_n i lvpecl receive sts-12/stm-4 clock - ne gative polarity pecl input - redundant port: this input pin, along with rxl_clkl_p functions as the recov - ered clock input, from a system back-plane or an optical trans - ceiver. the receiver sts-12/stm-4 interface block will sample the data applied at the rxldata_p/rxldata_n input pins, upon the falling edge of this signal. n ote : for aps (automatic protection switching) purposes, this input pin, along with rxl_clkl_r_ p functions as the redundant receive clock input port. k4 rxl_data_p i lvpecl receive sts-12/stm-4 data - positive polarity pecl input: this input pin, along with rxl_data_n functions as the recov - ered data input, from a system back-plane or an optical trans - ceiver. the receive sts-12/stm-4 interface block will sample the data applied to these input pins, upon the rising edge of the rxl_clkl_p (and the falling edge of the rxl_clkl_n) signals. n ote : for aps (automatic protection switching) purposes, this input pin, along with rx l_data_n functions as the primary receive data input port. l4 rxl_data_n i lvpecl receive sts-12/stm-4 data - ne gative polari ty pecl input: this input pin, along with rxl_data_p functions as the recov - ered data input, from a system back-plane or an optical trans - ceiver. the receive sts-12/stm-4 interface block will sample the data applied to these input pins, upon the rising edge of the rxl_clkl_p (and the falling edge of the rxl_clkl_n) signals. n ote : for aps (automatic protection switching) purposes, this input pin, along with rxl_da ta_p functions as the primary receive data input port. k3 rxl_data_r_p i lvpecl receive sts-12/stm-4 data - positive polarity pecl input - redundant port: this input pin, along with rxl_data_r_n functions as the recov - ered data input, from a system back-plane or an optical trans - ceiver. the receive sts-12/stm-4 interface block will sample the data applied to these input pins, upon the rising edge of the rxl_clkl_r_p (and the falling edge of the rxl_clkl_r_n) sig - nals. n ote : for aps (automatic protection switching) purposes, this input pin, along with rxl_data_r_n functions as the redundant receive data input port. sonet/sdh serial line interface pins p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 148 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper l3 rxl_data_r_n i lvpecl receive sts-12/stm-4 data - ne gative polarity pecl input - redundant port: this input pin, along with rxl_d ata_r_p functions as the recov - ered data input, from a system back-plane or an optical trans - ceiver. the receive sts-12/stm-4 interface block will sample the data applied to these input pins, upon the rising edge of the rxl_clkl_r_p (and the falling edge of the rxl_clkl_r_n) sig - nals. n ote : for aps (automatic protection switching) purposes, this input pin, along with rxl_data_r_n functions as the redundant receive data input port. t3 txl_clki_p i lvpecl transmit reference clock - positive polarity pecl input: this input pin, along with txl_clki_n can be configured to func - tion as the timing source for the sts-12/stm-4 transmit interface block. if these two input pins are configured to function as the timing source, then a 622.08mhz clock signal must be applied to these input pins in the form of a pecl signal. these two inputs can be configured to function as the timi ng source by writing the appropri - ate data into the interface cont rol register - by te 2 (indirect address = 0x00, 0x31), (direct address = 0x0131). t4 txl_clki_n i lvpecl transmit reference clock - negative polarity pecl input: this input pin, along with txl_clki_p can be configured to func - tion as the timing source for the sts-12/stm-4 transmit interface block. if these two input pins are configured to function as the timing source, then a 622.08mhz clock signal must be applied to these input pins in the form of a pecl signal. these two inputs can be configured to function as the timi ng source by writing the appropri - ate data into the interface cont rol register - by te 2 (indirect address = 0x00, 0x31), (direct address = 0x0131). n1 txl_data_p o lvpecl transmit sts-12/stm-4 data - po sitive polarity pecl output: this output pin, along with txl_da ta_n functions as the transmit data output, to the system back-plane (for transmission to some other system board) or an optical transceiver (for transmission to remote terminal equipment). for high-speed back-plane applications, it should noted that data is output from these output pins upon the rising/falling edge of txl_clko_p/txl_clko_n). n ote : for aps (automatic protection switching) purposes, this output pin, along with tx l_data_n functions as the primary transmit data output port. sonet/sdh serial line interface pins p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 149 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 n2 txl_data_n o lvpecl transmit sts-12/stm-4 data - negative polarity pecl output: this output pin, along with txl_ data_p functions as the transmit data output, to the system back-plane (for transmission to some other system board) or an optical transceiver (for transmission to remote terminal equipment). for high-speed back-plane applications, it should noted that data is output from these output pins upon the rising/falling edge of txl_clko_p/txl_clko_n). n ote : for aps (automatic protection switching) purposes, this output pin, along with txl_data_p functions as the primary transmit data output port. p1 txl_data_r_p o lvpecl transmit sts-12/stm-4 data - po sitive polarity pecl output - redundant port: this output pin, along with txl_data_r_n functions as the transmit data output, to the optical transceiver. for high-speed back-plane applications, it should noted that data is output from these output pins upon the rising/falling edge of txl_clko_r_p/txl_clko_r_n). n ote : for aps (automatic protection switching) purposes, this output pin, along with tx l_data_n functions as the redundant receive data input port. p2 txl_data_r_n o lvpecl transmit sts-12/stm-4 data - ne gative polarity pecl output - redundant port: this output pin, along with txl_data_r_p functions as the trans - mit data output, to the system back-plane (for transmission to some other system board) or an optical transceiver (for transmis - sion to remote terminal equipment). for high-speed back-plane applications, it should noted that data is output from these output pins upon the rising/falling edge of txl_clko_r_p/txl_clko_r_n). n ote : for aps (automatic protection switching) purposes, this output pin, along with txl_ data_r_p functions as the redundant transmit data output port. m1 txl_clko_p o lvpecl transmit sts-12/stm-4 clock - positive polarity pecl output: this output pin, along with txl_clko_n functions as the transmit clock output signal. these output pins are typically used in high- speed back-plane applications. in this case, outbound sts-12/ stm-4 data is output via the txl_data_p/txl_data_n output pins upon the rising edge of this clock signal. n ote : for aps (automatic protection switching) purposes, this output pin, along with txl_clko_n functions as the primary transmit output clock signal. sonet/sdh serial line interface pins p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 150 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper m2 txl_clko_n o lvpecl transmit sts-12/stm-4 clock - negative polarity pecl out - put: this output pin, along with txlclko_p functions as the transmit clock output signal. these output pins are typically used in high- speed back-plane applications. in this case, outbound sts-12/ stm-4 data is output via the txl_data_p/txl_data_n output pins upon the falling edge of this clock signal. n ote : for aps (automatic protection switching) purposes, this output pin, along with txl_clko_n functions as the primary transmit output clock signal. r1 txl_clko_r_p o lvpecl transmit sts-12/stm-4 clock - positive polarity pecl output - redundant port: this output pin, along with txl_clko_r_n functions as the transmit clock output signal. these output pins are typically used in high-speed back-plane applications. in this case, outbound sts-12/stm-4 data is output via the txl_data_r_p/ txl_data_r_n output pins upon the rising edge of this clock sig - nal. n ote : for aps (automatic protection switching) purposes, this output pin, along with txl_ clko_r_n functions as the redundant transmit output clock signal. r2 txl_clko_r_n o lvpecl transmit sts-12/stm-4 clock - negative polarity pecl output - redundant port: this output pin, along with txl_clko_r_p functions as the transmit clock output signal. these output pins are typically used in high-speed back-plane applications. in this case, outbound sts-12/stm-4 data is output via the txl_data_r_p/ txl_data_r_n output pins upon the rising edge of this clock sig - nal. for aps (automatic protection sw itching) purposes, this output pin, along with txl_clko_r_p functions as the redundant transmit output clock signal. sonet/sdh serial line interface pins p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 151 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 r4 refclk i ttl 77.76mhz or 622.08mhz clock synthesizer reference clock input pin: the function of this input pin depends upon whether or not the transmit sts-12/stm-4 clock synthesizer block is enabled. if clock synthesizer is enabled. if the transmit sts-12/stsm-4 clock synthesizer block is to be used to generate the 77.76mhz and /or 622.08mhz clock signal for the sts-12/stm-4 block, then a clo ck signal of either of the follow - ing frequencies, must be applied to this input pin. ? 12.96mhz ? 19.44mhz ? 51.84 mhz ? 77.76 mhz afterwards, the appropriate data needs to be written into the inter - face control register - byte 2 (indirect address = 0x00, 0x31), (direct address = 0x0131) in order to; (1) configure the clock synthesizer block to accept any of the above-mentioned signals and gener ate a 77.76mhz or 622.08mhz clock signal, (2) to configure the clock synthe sizer to function as the clock source for the sts-12/stm-4 block. if clock synthesizer is not enabled: if the transmit sts-12/stsm-4 clock synthesizer block is not to be used to generate the 77.76mhz and/or 622.08mhz clock signal for the sts-12/stm-4 block, then a 77.76mhz clock signal must be applied to this input pin. af6 los i ttl loss of optical carrier input - primary: the loss of carrier output (from the optical transceiver) should be connected to this input pin. if this input pin is pulled "high", then the receive sts-12 toh pro - cessor block will declare a loss of optical carrier condition. n ote : this input pin is only active if the primary port is active. this input pin is inactive if t he redundant port is active. ae6 los-r i ttl loss of optical carrier input - redundant: the loss of carrier output (from the optical transceiver) should be connected to this input pin. if this input pin is pulled "high", then the receive sts-12 toh pro - cessor block will declare a loss of optical carrier condition. n ote : this input pin is only active if the redundant port is active. this input pin is inactive if the primary port is active. sonet/sdh serial line interface pins p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 152 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ab7 exswitch o cmos external (aps) switch output pin: this output pin can be used to permit the xrt94l43 to perform aps externally. specifically, this output pin can be connected to some circuitry that permits the re-direction of sts-12/stm-4 traffic, should an aps event be needed. n ote : this output pin is disabled if the exswitchdis input pin number ab6 is pulled "high". ab6 exswitchdis i ttl external (aps) switch disable: this input pin permits the user to configure the xrt94l43 to per - form line aps switching internally or externally. 0 - configures the xrt94l43 to perform aps externally. in this mode, the xrt94l43 will execute an aps by toggling the state of the "exswitch" output pin. 1 - configures the xrt94l43 to perform aps internally. in this mode, each of the 12 receive sonet poh processor blocks (within the xrt94l43) will interna lly switch from processing the incoming sts-1 spe data from the primary receive sts-12 toh processor block, to now proce ssing the incoming sts-1 spe data from the redundant receive sts-12 toh processor block (or vice-versa). sonet/sdh serial line interface pins p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 153 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 sts-12/stm-4 telecom bus inte rface - transmit direction p in # s ignal n ame i/o s ignal t ype d escription g2 txa_clk o cmos transmit sts-12/stm-4 telecom bus interface - clock signal: this output clock signal functions as the clock source for the sts-12/ stm-4 transmit telecom bus. all output signals (on the transmit sts-12/stm-4 telecom bus) are updat ed upon the rising edge of this clock signal. this clock signal operates at 77.76mhz and is derived from the trans - mit clock synthesizer block. j1 txa_c1j1 o cmos sts-12/stm-4 transmit telecom bus - c1/j1 byte phase indicator output signal: this output pin pulses "high" under the following two conditions. 1. whenever the c1 byte is being output via the txa_ d[7:0] output, and 2. whenever the j1 byte is being output via the txa_ d[7:0] output. n otes : 1. the sts-12/stm-4 transmit telecom bus will indicate that it is transmitting the c1 byte (via the txa_d[7:0] output pins), by pulsing this output pin "high" (for one period of txa_clk) and keeping the txa_pl output pin pulled "low". 2. the sts-12/stm-4 transmit telecom bus will indicate that it is transmitting the j1 byte (via the txa_d[7:0] output pins), by pulsing this output pin "high" (for one period of txa_clk) while the txa_pl output pin is pulled "high". 3. this output pin is only acti ve if the sts-12/stm-4 telecom bus is enabled. j3 txa_alarm o cmos transmit sts-12/stm-4 telecom bus - alarm indicator output sig - nal: this output pin pulses "high", corresponding to any sts-1 signal (that is being output via the txa_d[7:0] output pins) is carrying the ais-p indicator. this output pin is "low" for all other conditions. h1 txa_dp o cmos sts-12/stm-4 transmit teleco m bus - parity output pin: this output pin can be configured to function as one of the following. 1. the even or odd parity value of the bits which are output via the txa_d[7:0] output pins. 2. the even or odd parity value of the bits which are being output via the txa_d[7:0] output pins and the states of the txa_pl and txa_c1j1 output pins. n ote : any one of these configuratio n selections can be made by writing the appropriate value into the telecom bus control register (indirect address = 0x00, 0x37), (direct address = 0x0137)..
xrt94l43 154 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper k5 txsbfp i ttl telecom bus sync reference input: if either the sts-12/stm-4 or any of the sts-3/stm-1 telecom bus interfaces are enabled, then an 8k hz pulse must be applied to this input pin. if the sts-12/stm-4 telecom bus interface is enabled: the transmit sts-12/stm-4 telecom bus interface will begin trans - mitting the very first byte of given sts-12 or stm-4 frame, upon sens - ing a rising edge (of the 8khz signal) at this input pin. if any of the sts-3/stm-1 telecom bus interfaces are enabled: the receive sts-3/stm-1 telecom bu s interfaces will begin transmit - ting the very first byte of a giv en sts-3 or stm-1 frame, upon sensing a rising edge (of the 8khz signal) at this input pin. n ote : if none of the telecom bus interfaces are used, then this pin should be tied to gnd. n otes : 1. 1.if this input pin is tied to gnd, then the transmit sts-12 toh processor block will generate its outbound sts-12/ stm-4 frames asynchronously with respect to any input signal. 2. this input signal must be synch ronized with the signal that is supplied to the refclk input pin. failure to insure this will result in bit errors being generated within the outbound sts- 12/stm-4 signal. 3. an 8khz pulse must be applied to this input pin, that has a width of approximately 12.8ns (one 77.76mhz clock period). do not apply a 50% duty cycle 8k hz signal to this input pin. sts-12/stm-4 telecom bus inte rface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 155 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 f3 txa_pl o cmos sts-12/stm-4 transmit telecom bu s - payload data indicator sig - nal: this output pin indicates whether or not toh transport overhead bytes are being output via th e txa_d[7:0] output pins. this output pin is pulled "low" for the duration that the sts-12/stm-4 transmit telecom bus is transmitting a transport overhead byte via the txa_d[7:0] output pins. conversely, this output pin is pull ed "high" for the duration that the sts-12/stm-4 transmit telecom bus is transmitting something other than a transport overhead byte (e.g., the poh or sts-1/sts-3c spe bytes) via the txa_d[7:0] output pins. g1 j5 j2 h5 e1 f2 f1 e3 txa_d0 txa_d1 txa_d2 txa_d3 txa_d4 txa_d5 txa_d6 txa_d7 o cmos sts-12/stm-4 transmit telecom bus - transmit output data bus pins: these 8 output pins function as the "sts-12/stm-4 transmit telecom bus" transmit output data bus. if the sts-12/stm-4 telecom bus interface is enabled, then all sts- 12/stm-4 data is output via these pins (in a byte-wide manner), upon the rising edge of the "txa_clk" output pin. n otes : 1. the pin txa_d7 will output the msb (most significant bit) of each byte that is output via the transmit sts-12/stm-4 telecom bus interface. 2. the pin txa_d0 will output the lsb (least significant bit) of each byte that is output via the transmit sts-12/stm-4 telecom bus interface. sts-12/stm-4 telecom bus inte rface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 156 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper sts-12/stm-4 telecom bus interface - receive direction p in # s ignal n ame i/o s ignal t ype d escription v4 rxd_clk i ttl receive sts-12/stm-4 telecom bus interface - clock signal: this input clock signal functions as the clock source for the receive sts- 12/stm-4 telecom bus interface. all receive sts-12/stm-4 telecom bus interface signals are sampled upon the rising edge of this input clock sig - nal. this clock signal should operate at 77.76mhz. n ote : this input pin is only used if the sts-12/stm-4 telecom bus has been enabled. it should be tied to gnd otherwise. u5 rxd_pl i ttl receive sts-12/stm-4 telecom bus interface - payload indicator sig - nal: this input pin indicates whether or not sts- 1/sts-3c spe bytes are being input via the rxd_d[7:0] input pins. this input pin should be pulled "high" coincident to whenever the receive sts-12/stm-4 telecom bus interface block is receiving sts-1/sts-3c spe data bytes via the rx d_d[7:0] i nput pins. conversely, this input pin should be pulled "low" coincident to whenever the receive sts-12/stm-4 telecom bus interface block is receiving something other th an an sts-1/sts-3c spe byte (e.g., a toh byte) via the rxd_d[7:0] input pins. n ote : the user should tie this pin to gnd if the sts-12/stm-4 telecom bus interface is configured to o perate in the re-phase on mode or is disabled.tie this pin to gnd if the sts-12/stm-4 telecom bus is not enabled. v2 rxd_c1j1 i ttl sts-12/stm-4 receive telecom bus c1/j1 byte phase indicator input signal: this input pin should be pulsed "high" during both of the following condi - tions. 1. whenever the c1 byte is being input to the receive sts-12/stm-4 tele - com bus interface - data bus input pins (rxd_d[7:0]). 2. whenever the j1 byte is being in put to the receive sts-12/stm-4 tele - com bus interface - databus input pins (rxd_d[7:0]). this input pin should be pulled "low" for all other times. n ote : tie this pin to gnd if the sts-12/stm-4 telecom bus is not enabled.
xrt94l43 157 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 u4 rxd_dp i ttl sts-12/stm-4 receive telecom bus - parity input pin: this input pin can be configured to function as one of the following. 1. the even or odd parity value of the bits which are input via the rxd_d[7:0] input pins. 2. the even or odd parity value of t he bits which are be ing input via the rxd_d[7:0] input and the states of the rxd_pl and rxd_c1j1 input pins. the receive sts-12/stm-4 telecom bus interface will use this pin to compute and verify the parity withi n the incoming sts-12/stm-4 data- stream. n otes : 1. any one of these configuration se lections can be made by writing the appropriate value into the telecom bus control register (indirect address = 0x00, 0x37, direct address = 0x0137. 2. tie this pin to gnd if the sts-12/stm-4 telecom bus interface is configured to operate in the re-p hase on mode or is disabled. t2 rxd_alarm i ttl receive sts-12/stm-4 telecom bus - alarm indicator input: this input pin pulses "high" corresponding to any sts-1 signal that is car - rying the ais-p indicator. more specifically, this input pin will be pulsed "high" coincident to when - ever a byte, corresponding to given sts- 1 signal (that is carrying the ais-p indicator) is being placed on the receive sts-12/stm-4 telecom bus - data bus input pins (rxd_d[7:0]). this input pin should be pulled "low" at all other times. n otes : 1. if the rxd_alarm input signal pulses "high" for any given sts-1 signal (within the incoming sts-12), then the xrt94l43 will automatically declare the ais-p defect for that particular sts-1 channel. 2. tie this pin to gnd if the sts-12/stm-4 telecom bus interface has been configured to operate in the re-phase on mode or is disabled. u3 v3 u2 t1 v5 u1 w1 v1 rxd_d0 rxd_d1 rxd_d2 rxd_d3 rxd_d4 rxd_d5 rxd_d6 rxd_d7 i ttl receive sts-12/stm-4 receive telecom bus - receive input data bus pins: these 8 input pins function as the "receive sts-12/stm4 receive tele - com bus" receive input data bus. all incoming sts-12/stm-4 data is sampled and latched (into the xrt94l43 via these input pins) upon the rising edge of the rxa_clk input pin. n otes : 1. 1.the user must insure that the msb (most significant bit) of each incoming byte is input to the rxd_d7 input pin. 2. the user must also insure that the lsb (least significant bit) of each incoming byte is input to the rxd_d0 input pin. 3. the user should tie these pins to gnd if the sts-12/stm-4 telecom bus is not enabled. sts-12/stm-4 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 158 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper sonet/sdh overhead interf ace - transmit direction p in # s ignal n ame i/o s ignal t ype d escription h2 txtohclk o cmos transmit toh input port - clock output: this output pin, along with the tx tohenable, txtohframe output pins and the txtoh and txtohins input pins function as the transmit toh input port. the transmit toh input port allows t he user to insert their own value for the toh bytes (in the outbound sts-12/stm-4 signal). this output pin provides a clock sign al. if the txtohenable output pin is "high" and if the txtohins input pin is pulled "high", then the user is expected to provide a given bit (withi n the toh) to the txtoh input pin, upon the falling edge of this clock signal. the data, residing on the txtoh input pin will be latched into the xrt94l43 upon the rising edge of this clock signal. n ote : the transmit toh input port only support the insertion of the toh within the first sts-1, wit hin the outbound sts-12 signal. h4 txtohenable o cmos transmit toh input port - toh enable (or ready) indicator: this output pin, along with the tx tohclk, txtohframe output pins and the txtoh and txtohins input pins function as the transmit toh input port. this output pin will toggle and remain "high" anytime the transmit toh input port is ready to externally accept toh data. if it is desired to externally insert a value of toh into the outbound sts- 12 data stream via the transmit toh input port, then do the following: ? continuously sample the state of txtohframe and this output pin upon the rising edge of txtohclk. ? whenever this output pin pulses "high", then the user's external circuitry should drive the txtohins input pin "high". ? next, the user should output the next toh bit, onto the txtoh input pin, upon the falling edge of txtohclk. d1 txtoh i ttl transmit toh input port - input pin: this input pin, along with the tx tohins input pin, the txtohenable and txtohframe and txtohclk output pins function as the transmit toh input port. if it is desired to externally insert a value of toh into the outbound sts- 12 data stream via the transmit toh input port, then do the following: ? continuously sample the state of txtohframe and txtohenable upon the rising edge of txtohclk. ? whenever txtohenable pulses " high", then the user's external circuitry should drive the txtohins input pin "high". ? next, the user should output the next toh bit, onto this input pin, upon the falling edge of txtohclk. the transmit toh input port will sample the data (on this input pin) upon the rising edge of txtohclk. n ote : data at this input pin will be ignored (e.g., not sampled) unless the txtohenable output pin is "high" and the txtohins input pin is pulled "high".
xrt94l43 159 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 g4 txtohframe o cmos transmit toh input port - sts-12/stm-4 frame indicator: this output pin, along with txto hclk, txtohenable output pins, and the txtoh and txtohins input pins function as the transmit toh input port. this output pin will pulse "high" (f or one period of txtohclk), one txtohclk clock period prior to the first toh bit of a given sts-12 frame, being expected vi a the txtoh input pin. if it is desired to externally insert a value of toh into the outbound sts- 12 data stream via the transmit toh input port, then do the following: ? continuously sample the state of txtohenable and this output pin upon the rising edge of txtohclk. ? whenever the txtohenable output pi n pulse "high", then the user's external circuitry should drive the txtohins input pin "high". ? next, the user should output the next toh bit, onto the txtoh input pin, upon the falling edge of txtohclk. n ote : the external circuitry (which is being interfaced to the transmit toh input port can use this output pin to denote the boundary of sts-12 frames. c1 txtohins i ttl transmit toh input port - insert enable input pin: this input pin, along with the tx toh input pin, and the txtohenable, txtohframe and txtohclk output pins function as the transmit toh input port. this input pin is used to either enable or disable the transmit toh input port. if this input pin is "low", then the transmit toh input port will be dis - abled and will not sample and insert (into the outbound sts-12 data stream) any data residing on the txtoh input, upon the rising edge of txtohclk. if this input pin is "high", then the transmit toh input port will be enabled. in this mode, whenever th e txtohenable output pin is also "high", the transmit toh input port will sample and latch any data that is presented on the txtoh input pin, upon the rising edge of txtohclk. if it is desired to externally insert a value of toh into the outbound sts- 12 data stream via the transmit toh input port, then do the following: ? continuously sample the state of txtohframe and txtohenable upon the rising edge of txtohclk. ? whenever the txtohenable output pin is sampled "high" then the user's external circuitry should drive this input pin "high". ? next, the user should output the next toh bit, onto the txtoh input pin, upon the falling edge of txto hclk. the transmit toh input port will sample the data (on this input pin) upon the rising edge of txtohclk. n ote : data applied to the txtoh input pin will be ignored (e.g., not sampled) unless then the txtohenable and this input pin are each "high". sonet/sdh overhead interf ace - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 160 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper g3 txldccenable o cmos transmit - line dcc input port - enable output pin: this output pin, along with the txtohclk output pin and the txldcc input pin are used to insert the value for the d4, d5, d6, d7, d8, d9, d10, d11 and d12 bytes into the transmit sts-12 toh processor block. the transmit sts-12 toh processor block will accept this data and will insert into the d4, d5, d6, d7, d8, d9, d10, d11 and d12 byte- fields, within the outbound sts-12 data-stream. the line dcc hdlc controller circuitr y (which is connected to the txtohclk, the txldcc and this output pin, is suppose to do the follow - ing. 1. it should continuously monito r the state of this output pin. 2. whenever this output pin pulses "high", then the line dcc hdlc controller circuitry should place the next line dcc bit (to be inserted into the transmit sts-12 toh processor block) onto the txldcc input pin, upon the falling edge of txtohclk. 3. any data that is placed on the txldcc input pin, will be sampled upon the rising edge of txohclk. j4 txsdccenable o cmos transmit - section dcc input port - enable output pin: this output pin, along with the tx tohclk output pin and the txsdcc input pin are used to insert the value for the d1, d2 and d3 bytes, into the transmit sts-12 toh processor block. the transmit sts-12 toh processor block will accept this data and will insert into the d1, d2 and d3 byte-fields, within th e outbound sts-12 data-stream. the section dcc hdlc controller circuitry (which is connected to the txtohclk, the txsdcc and this output pin, is suppose to do the follow - ing. 1. it should continuously monito r the state of this output pin. 2. whenever this output pin pulses "high", then the section dcc hdlc controller circuitry should place the next section dcc bit (to be inserted into the transmit sts-12 toh processor block) onto the txsdcc input pin, upon the falling edge of txtohclk. 3. any data that is placed on the txsdcc input pin, will be sampled upon the rising edge of txohclk. e2 txsdcc i ttl transmit - section dcc input port - input pin: this input pin, along with the txsdccenable and the txtohclk output pins are used to insert a value for the d1, d2 and d3 bytes, into the transmit sts-12 toh processor block. the transmit sts-12 toh processor block will accept this data and insert it into the d1, d2 and d3 byte fields, within the outbound sts-12 data-stream. the section dcc hdlc circuitry that is interfaced to this input pin, the txsdccenable and the txtohclk pins is suppose to do the following. 1. it should continuously monitor the state of the txsdccenable input pin. 2. whenever the txsdccenable input pin pulses "high", then the sec - tion dcc hdlc controller circuitry should place the next section dcc bit (to be inserted into the transmit sts-12 toh processor block) onto this input pin upon the falling edge of txtohclk. 3. any data that is placed on the txsdcc input pin, will be sampled upon the rising edge of txtohclk. n ote : tie this pin to gnd if it is not going to be used. sonet/sdh overhead interf ace - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 161 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 h3 txldcc i ttl transmit - line dcc input port: this input pin, along with the txldccenable and the txtohclk pins are used to insert a value for the d4, d5, d6, d7, d8, d9, d10, d11 and d12 bytes, into the transmit sts-12 toh processor block. the trans - mit sts-12 toh processor block will accept this data and insert it into the d4, d5, d6, d7, d8, d9, d10, d1 1 and d12 byte-fields, within the outbound sts-12 data-stream. whatever line dcc hdlc controller circu itry is interface to the this input pin, the txldccenable and t he txtohclk is suppose to do the following. 1. it should continuously monitor t he state of the txldccenable input pin. 2. whenever the txldccenable input pin pulses "high", then the sec - tion dcc interface circuitry should place the next line dcc bit (to be inserted into the transmit sts-12 toh processor block) onto the txldcc input pin, upon the falling edge of txtohclk. 3. any data that is placed on the txldcc input pin, will be sampled upon the rising edge of txtohclk. n ote : tie this pin to gnd, if it is not going to be used. f4 txe1f1e2enable o cmos transmit e1-f1-e2 byte input port - enable (or ready) indicator output pin: this output pin, along with the tx tohclk output pin and the txe1f1e2 input pin are used to insert a value fo r the e1, f1 and e2 bytes, into the transmit sts-12 toh processor block. the transmit sts-12 toh processor block will accept this data and will insert into the e1, f1 and e2 byte-fields, within the outbound sts-12 data-stream. whatever external circuitry (which is connected to the txtohclk, the txe1f1e2 and this output pin, is suppose to do the following. 1. it should continuously monito r the state of this output pin. 2. whenever this output pin pulses "high", then the external circuitry should place the next orderwire bit (to be inserted into the transmit sts-12 toh processor block) onto the txe1f1e2 input pin, upon the falling edge of txtohclk. any data that is placed on the txe1f1e2 input pin, will be sampled upon the rising edge of txohclk. d2 txe1f2e2frame o cmos transmit e1-f1-e2 byte inpu t port - framin g output pin: this output pin pulses "high" for one period of txtohclk, one txto - hclk bit-period prior to the transmit e1-f1-e2 byte input port expecting the very first byte of the e1 byte , within a given outbound sts-12 frame. sonet/sdh overhead interf ace - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 162 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper j6 txe1f1e2 i ttl transmit e1-f1-e2 byte input port - input pin: this input pin, along with the txe1f1e2enable and the txtohclk out - put pins are used to insert a value for the e1, f1 and e2 bytes, into the transmit sts-12 toh processor block. the transmit sts-12 toh processor block will accept this data and insert it into the e1, f1 and e2 byte fields, within the outbound sts-12 data-stream. whatever external circuitry that is interfaced to this input pin, the txe1f1e2enable and the txtohclk pins is suppose to do the follow - ing. 1. it should continuously monitor the state of the txe1f1e2enable input pin. 2. whenever the txe1f1e2enable input pin pulses "high", then the external circuitry should place the next orderwire bit (to be inserted into the transmit sts-12 toh processor bl ock) onto this input pin upon the falling edge of txtohclk. 3. any data that is placed on the txe1f1e2 input pin, will be sampled upon the rising edge of txtohclk. n ote : tie this pin to gnd if it is not going to be used. sonet/sdh overhead interf ace - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 163 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 c10 b13 ad12 ad8 a16 d18 ad13 ae8 d13 c18 ae17 ab12 d9 c13 ae11 af4 txpoh_0 txpoh_1 txpoh_2 txpoh_3 txpoh_4 txpoh_5 txpoh_6 txpoh_7 txpoh_8 txpoh_9 txpoh_10 txpoh_11 txpoh_12 txpoh_13 txpoh_14 txpoh_15 i ttl transmit path overhead input port - input pin. these input pins allow the following actions. 1. insertion oft the poh data into each of the 12 transmit sonet poh processor blocks (for insertion and transmission via the outbound sts- 12 signal. 2. insertion of the poh data into each of the 12 transmit sts-1 poh processor blocks (for insertion and transmission via each of the out - bound sts-1 signals). 3. insertion of the toh data into each of the 12 transmit sts-1 toh processor blocks (for insertion and transmission via each of the out - bound sts-1 signals). the function of these input pins, depends upon whether or not the toh data is inserted into the 12 tr ansmit sts-1 toh processor blocks. if the user is only inserting poh data via these input pins: in this mode, the external circuitr y (which is being interfaced to the transmit path overhead input port is suppose to monitor the following output pins. ? txpohframe_n ? txpohenable_n ? txpohclk_n the txpohframe_n output pin will toggle "high" upon the falling edge of txpohclk_n approximately one txpohclk_n period prior to the txpoh port being ready to accept and process the first bit within the j1 byte (e.g., the first poh byte). the txpohframe_n output pin will remain "high" for eight consecutiv e txpohclk_n periods. the external circuitry should use this pin to note sts- 1 spe frame boundaries. the txpohenable_n output pin will toggle "high" upon the falling edge of txpohclk_n approximately one txpohclk_n period prior to the txpoh port being ready to accept and process the first bit within a given poh byte. to externally insert a given poh by te, (1) assert the txpohins_n input pin by toggling it "high" and (2) place the value of the first bit (within this particular poh byte) on this input pin upon the very next falling edge of txpohclk_n. this data bit will be sampled upon the very next rising edge of txpohclk_n. the external circ uitry should continue to keep the txpohins_n input pin "high" and adv ancing the next bits (within the poh bytes) upon each falling edge of txpohclk_n. if the user is inserting both poh and toh data via these input pins: in this mode, the external circuitr y (which is being interfaced to the transmit path overhead input port is suppose to monitor the following output pins. ? txpohframe_n ? txpohenable_n ? txpohclk_n (continued below) sonet/sdh overhead interf ace - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 164 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper c10 b13 ad12 ad8 a16 d18 ad13 ae8 d13 c18 ae17 ab12 d9 c13 ae11 af4 txpoh_0 txpoh_1 txpoh_2 txpoh_3 txpoh_4 txpoh_5 txpoh_6 txpoh_7 txpoh_8 txpoh_9 txpoh_10 txpoh_11 txpoh_12 txpoh_13 txpoh_14 txpoh_15 i ttl if the user is inserting both poh and toh data via these input pins: (continued) the txpohframe_n output pin will togg le "high" twice during a given sts-1 frame period. first, this outpu t pin will toggle "high" coincident with the txpoh port being ready to accept and process the a1 byte (e.g., the very first toh byte). second, this output pin will toggle "high" coincident with the txpoh port being ready to accept and process the j1 byte (e.g., the very first poh byte). if the externally circuitry samples the txpohframe_n output pin "high", and the txpohenable_n output pin " low", then the txpoh port is now ready to accept and process the very first toh byte. if the externally circuitry samples the txpohframe_n output pin "high" and the txpohenable_n output pin " high", then the txpoh port is now ready to accept and process the very first poh byte. to externally insert a given poh or toh byte, do the following; (1) assert the txpohins_n input pin by toggling it "high" and, (2) place the value of the first bit (within this particular poh or toh byte) on this input upon the very next falling edge of txpohclk_n. this data bit will be sampled upon the very next rising edge of txpohclk_n. the external circuitry should continue to keep the txpohins_n input pin "high" and adv ancing the next bits (within the poh bytes) upon each falling edge of txpohclk_n. n otes : 1. if poh data is externally inserted into each of the 12 transmit sonet poh processor blocks, th en these input pins cannot be used to externally insert poh data into each of the 12 transmit sts-1 poh processor blocks. 2. toh data can be externally inserted into each of the 12 transmit sts-1 toh processor blocks, only if poh data is not externally inserted into each of the 12 transmit sonet poh processor blocks. b10 a15 ac13 ad9 b16 d19 ae13 ae9 d14 c19 af19 ab13 e10 c14 af11 af5 txpohclk_0 txpohclk_1 txpohclk_2 txpohclk_3 txpohclk_4 txpohclk_5 txpohclk_6 txpohclk_7 txpohclk_8 txpohclk_9 txpohclk_10 txpohclk_11 txpohclk_12 txpohclk_13 txpohclk_14 txpohclk_15 o cmos transmit path overhead input port - clock output pin: these output pins, along with txpoh_n, txpohenable_n, txpohins_n and txpohframe_n func tion as the transmit path over - head (txpoh) input port. the txpohframe_n and txpohenable_n output pins are updated upon the falling edge this clock output signal. the txpohins_n input pins and the data residing on the txpoh_n input pins are sampled on the rising edge of this clock signal. sonet/sdh overhead interf ace - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 165 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 a6 a11 ac12 ad7 d8 b12 af14 ab10 a12 c17 aa15 ac10 d7 e11 ac11 ad6 txpohframe_0 txpohframe_1 txpohframe_2 txpohframe_3 txpohframe_4 txpohframe_5 txpohframe_6 txpohframe_7 txpohframe_8 txpohframe_9 txpohframe_10 txpohframe_11 txpohframe_12 txpohframe_13 txpohframe_14 txpohframe_15 o cmos transmit path overhead input port - frame output pin: these output pins, along with the txpoh_n, txpohenable_n, txpohins_n and txpohclk_n function as the transmit path overhead input port. the function of these output pins depends upon whether poh or toh data is inserted via the txpoh_n input pins. if the user is only inserting poh data via these input pins: in this mode, the txpoh port will pu lse these output pins "high" when - ever it is ready to accept and proces s the j1 byte (e.g., the very first poh byte) via this port. if the user is inserting both poh and toh data via these input pins: in this mode, the txpoh port will pu lse these output pins "high" coinci - dent with the following. 1. whenever the txpoh port is ready to accept and process the a1 byte (e.g., the very first toh byte) via this port. 2. whenever the txpoh port is ready to accept and process the j1 byte (e.g., the very first poh byte) via this port. n ote : the external circuitry can dete rmine whether the txpoh port is expecting the a1 byte or the j1 byte, by checking the state of the corresponding txpohenable output pin. if the txpohenable_n output pin is "low" while the txpohframe_n output pin is "high", then the txpoh port is ready to process the a1 (toh) bytes. if the txpohenable_n output pin is "high" while the txpohframe_n output pin is "high", then the txpoh port is ready to process the j1 (poh) bytes. sonet/sdh overhead interf ace - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 166 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper a7 c12 ae12 ac9 e9 a13 af16 ab11 e13 d17 ac16 af8 e8 e12 af9 ac8 txpohins_0 txpohins_1 txpohins_2 txpohins_3 txpohins_4 txpohins_5 txpohins_6 txpohins_7 txpohins_8 txpohins_9 txpohins_10 txpohins_11 txpohins_12 txpohins_13 txpohins_14 txpohins_15 i ttl transmit path overhead input port - insert enable input pin: these input pins, along wit h txpoh_n, txpohenable_n, txpohframe_n and txpohclk_n function as the transmit path over - head (txpoh) input port. these input pins are used to enable or disable the txpoh input port. if these input pins are pulled "high" , then the txpoh port will sample and latch data via the corresponding txpoh input pins, upon the rising edge of txpohclk_n. conversely, if these input pins ar e pulled "low", then the txpoh port will not sample and latch data via the corresponding txpoh input pins. n ote : if the txpohins_n input pin is pu lled "low", this setting will be overridden if, the transmit sonet/sts-1 poh processor or transmit sts-1 toh processor blo cks are configured to accept certain poh or toh overhead bytes via the external port. d10 d15 ab14 ae7 a10 a17 ac14 af7 c11 b14 ad14 ae10 b11 d16 af13 ab9 txpohenable_0 txpohenable_1 txpohenable_2 txpohenable_3 txpohenable_4 txpohenable_5 txpohenable_6 txpohenable_7 txpohenable_8 txpohenable_9 txpohenable_10 txpohenable_11 txpohenable_12 txpohenable_13 txpohenable_14 txpohenable_15 o cmos transmit path overhead input port - poh indicator output pin: these output pins, along with txpoh_ n, txpohins_n, txpohframe_n and txpohclk_n function as the transmit path overhead (txpoh) input port. these output pins will pulse "high" anytime the txpoh port is ready to accept and process poh bytes. th ese output pins will be "low" at all other times. sonet/sdh overhead interf ace - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 167 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 sts-3/stm-1 telecom bus interface - transmit direction p in # s ignal n ame i/o s ignal t ype d escription e15 sts3txa_clk_0 txsbclk_0 dmo_0 i ttl sts-3 transmit telecom bus clock input/stm-1 sub-rate clock/dmo_0 (general purpose) input pin: the function of this input pin depen ds upon whether or not thests-3/ stm-1 telecom bus interface for channel 0 has been enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3 transmit telecom bus transmit clock input - channel 0: this input clock signal functions as the clock source for the sts-3/ stm-1 transmit telecom bus, associated with channel 0. all input signals (e.g., sts3txa_alarm_0, sts3txa_d_0[7:0], sts3txa_dp_0, sts3txa_pl_0, sts3txa_c1j1_0) are sampled upon the falling edge of this input clock signal. this clock signal should operate at 19.44mhz. if sts-3/stm-1 telecom bus (cha nnel 0) is disabled - dmo_0 (general purpose) input pin: this input pin can be used as a general purpose input pin. the state of this input pin can be determined by reading the state of bit 2 (dmo) within the line interface scan register associated with channel 0 (address = 0x1e, 0x81), (direct address = 0x1f81). n ote : for product legacy purposes, this pin is called dmo_0, because one possible application is to tie this input pin to a dmo (drive monitor output) outp ut pin, from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this input pin, and the corresponding register bit can be used for any purpose. c26 sts3txa_clk_1 txsbclk_1 dmo_1 i ttl sts-3 transmit telecom bus clock input/stm-1 sub-rate clock/dmo_1 (general purpose) input pin: the function of this input pin depen ds upon whether or not thests-3/ stm-1 telecom bus interface for channel 1 has been enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3 transmit telecom bus clock input - channel 1: this input clock signal functions as the clock source for the sts-3/ stm-1 transmit telecom bus, associated with channel 1. all input signals, (e.g., sts3txa_alarm_1, sts3txa_d_1[7:0], sts3txa_dp_1, sts3txa_pl_1, sts3txa_c1j1_1) are sampled upon the falling edge of this input clock signal. this clock signal should operate at 19.44mhz. if sts-3/stm-1 telecom bus (cha nnel 1) is disabled - dmo_1 (general purpose) input pin: this input pin can be used as a general purpose input pin. the state of this input pin can be determined by reading the state of bit 2 (dmo) within the line interface scan register associated with channel 1 (address = 0x2e, 0x81), (direct address = 0x2f81). n ote : for product legacy purposes, this pin is called dmo_1 because one possible application is to tie this input pin to a dmo (drive monitor output) outp ut pin, from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this input pin, and the corresponding register bit can be used for any purpose.
xrt94l43 168 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ae25 sts3txa_clk_2 txsbclk_2 dmo_2 i ttl sts-3 transmit telecom bus clock input/stm-1 sub-rate clock/dmo_2 (general purpose) input pin: the function of this input pin depen ds upon whether or not thests-3/ stm-1 telecom bus interface for channel 2 has been enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3 transmit telecom bus transmit clock input - channel 2: this input clock signal functions as the clock source for the sts-3/ stm-1 transmit telecom bus, associated with channel 2. all input signals, (e.g., sts3txa_alarm_2, sts3txa_d_2[7:0], sts3txa_dp_2, sts3txa_pl_2, sts3txa_c1j1_2) are sampled upon the falling edge of this input clock signal. this clock signal should operate at 19.44mhz. if sts-3/stm-1 telecom bus (cha nnel 2) is disabled - dmo_2 - drive monitor output input (from xrt73l0x liu ic) - channel 2: this input pin can be used as a general purpose input pin. the state of this input pin can be determined by reading the state of bit 2 (dmo) within the line interface scan register associated with channel 2 (indirect address = 0x3e, 0x81), (direct address = 0x3f81). n ote : for product legacy purposes, this pin is called dmo_2 because one possible application is to tie this input pin to a dmo (drive monitor output) out put pin, from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this input pin, and the corresponding register bit can be used for any purpose. ad17 sts3txa_clk_3 txsbclk_3 dmo_3 i ttl sts-3 transmit telecom bus clock input/stm-1 sub-rate clock/dmo_3 (general purpose) input pin: the function of this input pin depen ds upon whether or not thests-3/ stm-1 telecom bus interface for channel 3 has been enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3 transmit telecom bus clock input - channel 3: this input clock signal functions as the clock source for the sts-3/ stm-1 transmit telecom bus, associated with channel 3. all input signals (e.g., sts3txa_alarm_3, sts3txa_d_3[7:0], sts3txa_dp_3, sts3txa_pl_3, sts3txa_c1j1_3) are sampled upon the falling edge of this input clock signal. this clock signal should operate at 19.44mhz. if sts-3/stm-1 telecom bus (cha nnel 3) is disabled - dmo_3 (general purpose) input pin: this input pin can be used as a general purpose input pin. the state of this input pin can be determined by reading the state of bit 3 (dmo) within the line interface scan register associated with channel 3 (address = 0x4e, 0x81), (direct address = 0x4f81). n ote : for product legacy purposes, this pin is called dmo_3, because one possible application is to tie this input pin to a dmo (drive monitor output) out put pin, from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this input pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 169 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 e14 sts3txa_pl_0 txsbframe_0 rlol_0 i ttl sts-3/stm-1 transmit telecom bu s - payload indicator signal - channel 0/rlol_0 (general purpose) input pin: the function of this input depends upon whether or not thests-3/ stm-1 telecom bus interface for channel 0 has been enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bu s - payload indicator signal - channel 0: this input pin indicates whether or not transport overhead (toh) bytes are being input via th e txa_d_0[7:0] input pins. this input pin should be pulled "low" for the duration that the sts-3/ stm-1 transmit telecom bus is receiving a toh byte, via the txa_d_0[7:0] input pins. n ote : this input signal is sampled upon the falling edge of sts3txa_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - rlol_0 (general purpose) input pin. this input pin can be used as a general purpose input pin. the state of this input pin can be determined by reading the state of bit 1 (rlol) within the line interface scan register associated with channel 0 (address = 0x1e, 0x81), (direct address = 0x1f81). n ote : for product legacy purposes, this pin is called rlol_0 because one possible application is to tie this input pin to a rlol (receive loss of lock) out put pin, from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this input pin and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 170 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper a26 sts3txa_pl_1 txsbframe_1 rlol_1 i ttl sts-3/stm-1 transmit telecom bu s - payload indicator signal - channel 1/rlol_1 (general purpose) input pin: the function of this input pin depen ds upon whether or not thests-3/ stm-1 telecom bus interface for channel 1 has been enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bu s - payload indicator signal - channel 1: this input pin indicates whether or not transport overhead (toh) bytes are being input via th e txa_d_1[7:0] input pins. this input pin should be pulled "low" for the duration that the sts-3/ stm-1 transmit telecom bus is receiving a toh byte, via the txa_d_1[7:0] input pins. n ote : this input signal is sampled upon the falling edge of sts3txa_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - rlol_1 (general purpose) input pin: this input pin can be used as a general purpose input pin. the state of this input pin can be determined by reading the state of bit 1 (rlol) within the line interface scan register associated with channel 1 (indirect address = 0x2e, 0x81), (direct address = 0x2f81). n ote : for product legacy purposes, this pin is called rlol_1 because one possible application is to tie this input pin to a rlol (receive loss of lock) out put pin, from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this input pin and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 171 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ad25 sts3txa_pl_2 txsbframe_2 rlol_2 i ttl sts-3/stm-1 transmit telecom bu s - payload indicator signal - channel 2/rlol_2 (general purpose) input pin: the function of this input pin depen ds upon whether or not thests-3/ stm-1 telecom bus interface for channel 2 has been enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bu s - payload indicator signal - channel 2: this input pin indicates whether or not transport overhead (toh) bytes are being input via th e txa_d_2[7:0] input pins. this input pin should be pulled "low" for the duration that the sts-3/ stm-1 transmit telecom bus is receiving a toh byte, via the txa_d_2[7:0] input pins. n ote : this input signal is sampled upon the falling edge of sts3txa_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - rlol_2 (general purpose) input pin: this input pin can be used as a general purpose input pin. the state of this input pin can be determined by reading the state of bit 1 (rlol) within the line interface scan register associated with channel 2 (indirect address = 0x3e, 0x81), (direct address = 0x3f81). n ote : for product legacy purposes, this pin is called rlol_2 because one possible application is to tie this input pin to a rlol (receive loss of lock) out put pin, from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this input pin and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 172 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ab17 sts3txa_pl_3 txsbframe_3 rlol_3 i ttl sts-3/stm-1 transmit telecom bu s - payload indicator signal - channel 3/rlol_3 (general purpose) input pin: the function of this input pin depen ds upon whether or not thests-3/ stm-1 telecom bus interface for channel 3 has been enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bu s - payload indicator signal - channel 3: this input pin indicates whether or not transmit overhead (toh) bytes are being input via th e txa_d_3[7:0] input pins. this input pin should be pulled "low" for the duration that the sts-3/ stm-1 transmit telecom bus is receiving a toh byte, via the txa_d_3[7:0] input pins. n ote : this input signal is sampled upon the falling edge of sts3txa_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - rlol_3 (general purpose) input pin: this input pin can be used as a general purpose input pin. the state of this input pin can be determined by reading the state of bit 1 (rlol) within the line interface scan register associated with channel 3 (indirect address = 0x4e, 0x81), (direct address = 0x4f81). n ote : for product legacy purposes, this pin is called rlol_3 because one possible application is to tie this input pin to a rlol (receive loss of lock) out put pin, from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this input pin and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 173 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 b24 sts3txa_c1j1_0 txds3fp_8 txsts1pl_8 txsbframe_0 i/o ttl/ cmos sts-3/stm-1 transmit telecom bus c1/j1 byte phase indicator input signal (channel 0); ds3/e3 frame generator framing pulse input/output pin - channel 8: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface for channel 0 has been enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bus c1/j1 byte phase indicator input signal (channel 0): this input pin should be pulsed "high" during both of the following conditions. 1. whenever the c1 byte is being input to the sts-3/stm-1 transmit telecom bus (txa_d_0[7:0]) input pins. 2. whenever the j1 byte is being input to the sts-3/stm-1 transmit telecom bus (txa_d_0[7:0]) input pins. if sts-3/stm-1 telecom bus (channel 0) is disabled - txds3fp_8 (transmit ds3 frame pulse input/outp ut - channel 8): if the sts-3/stm-1 telecom bus (channel 0) is disabled and if the ds3/e3 framer block is enabled then this pin will function as either a transmit framing reference input pin or as a transmit framing ref - erence output pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the loop-timing or in the local-timing/ asynchronous framing mode: this pin will function as a frami ng reference output pin. the frame generator block (associated with channel 8) will pulse this output pin "high" for one ds3/e3 bit-period, one period prior to the first bit of a given ds3 or e3 frame being applied to the ds3/e3/ sts1_data_in_8 input pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the local-timing/txds3fp mode: this pin will function as a framing reference input pin. in this mode, the user is expected to pulse this input pin "high" for one ds3 or e3 bit-period, coincident with the first bit of a given ds3 or e3 frame, being placed on the ds3/e3/sts1_data_in_8 input pin. the frame generator block (associated with channel 8) will synchronize its gen - eration of ds3 or e3 frames to t hese framing pulses applied to this input pin. n ote : this pin is inactive if the frame generator block, associated with channel 8 is by-passed. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 174 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper j23 sts3txa_c1j1_1 txds3fp_9 txsbframe_1 i/o ttl/ cmos sts-3/stm-1 transmit telecom bus c1/j1 byte phase indicator input signal (channel 1); ds3/e3 frame generator framing pulse input/output pin - channel 9: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface for channel 1 has been enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus c1/j1 byte phase indicator input signal (channel 1): this input pin should be pulsed "high" during both of the following conditions. 1. whenever the c1 byte is being input to the sts-3/stm-1 transmit telecom bus (txa_d_1[7:0]) input pins. 2. whenever the j1 byte is being input to the sts-3/stm-1 transmit telecom bus (txa_d_1[7:0]) input pins. if sts-3/stm-1 telecom bus (channel 1) is disabled - txds3fp_9 (transmit ds3 frame pulse input/outp ut - channel 9): if the sts-3/stm-1 telecom bus (channel 1) is disabled and if the ds3/e3 framer block is enabled then this pin will function as either a transmit framing reference input pin or as a transmit framing ref - erence output pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the loop-timing or in the local-timing/ asynchronous framing mode: this pin will function as a frami ng reference output pin. the frame generator block (associated with cha nnel 9) will pulse this output pin "high" for one ds3/e3 bit-period, one period prior to the first bit of a given ds3 or e3 frame being applied to the ds3/e3/ sts1_data_in_9 input pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the local-timing/txds3fp mode: this pin will function as a framing reference input pin. in this mode, the user is expected to pulse this input pin "high" for one ds3 or e3 bit-period, coincident with the firs t bit of a given ds3 or e3 frame, being placed on the ds3/e3/sts1_data_in_9 input pin. the frame generator block (associated with channel 9) will synchronize its gen - eration of ds3 or e3 frames to t hese framing pulses applied to this input pin. n ote : this pin is inactive if the fr ame generator block, associated with channel 9 is by-passed. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 175 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 af24 sts3txa_c1j1_2 txds3fp_10 txsts1pl_10 txsbframe_2 i/o ttl/ cmos sts-3/stm-1 transmit telecom bus c1/j1 byte phase indicator input signal (channel 2); ds3/e3 frame generator framing pulse input/output pin - channel 10: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface for channel 2 has been enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus c1/j1 byte phase indicator input signal (channel 2): this input pin should be pulsed "high" during both of the following conditions. 1. whenever the c1 byte is being input to the sts-3/stm-1 transmit telecom bus (txa_d_2[7:0]) input pins. 2. whenever the j1 byte is being input to the sts-3/stm-1 transmit telecom bus (txa_d_2[7:0]) input pins. if sts-3/stm-1 telecom bus (channel 2) is disabled - txds3fp_10 (transmit ds3 frame pulse input/outp ut - channel 10): if the sts-3/stm-1 telecom bus (channel 2) is disabled and if the ds3/e3 framer block is enabled then this pin will function as either a transmit framing reference input pin or as a transmit framing ref - erence output pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the loop-timing or in the local-timing/ asynchronous framing mode: this pin will function as a frami ng reference output pin. the frame generator block (associated with channel 10) will pulse this output pin "high" for one ds3/e3 bit-period, one period prior to the first bit of a given ds3 or e3 frame being applied to the ds3/e3/ sts1_data_in_10 input pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the local-timing/txds3fp mode: this pin will function as a framing reference input pin. in this mode, the user is expected to pulse this input pin "high" for one ds3 or e3 bit-period, coincident with the first bit of a given ds3 or e3 frame, being placed on the ds3/e3/sts1_data_in_10 input pin. the frame generator block (associated with channel 10) will synchro - nize its generation of ds3 or e3 frames to these framing pulses applied to this input pin. n ote : this pin is inactive if the frame generator block, associated with channel 10 is by-passed. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 176 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper af17 sts3txa_c1j1_3 txds3fp_11 txsts1pl_11 txsbframe_3 i/o ttl/ cmos sts-3/stm-1 transmit telecom bus c1/j1 byte phase indicator input signal (channel 3); ds3/e3 frame generator framing pulse input/output pin - channel 11: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface for channel 11 has been enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus c1/j1 byte phase indicator input signal (channel 3): this input pin should be pulsed "high" during both of the following conditions. 1. whenever the c1 byte is being input to the sts-3/stm-1 transmit telecom bus (txa_d_3[7:0]) input pins. 2. whenever the j1 byte is being input to the sts-3/stm-1 transmit telecom bus (txa_d_3[7:0]) input pins. if sts-3/stm-1 telecom bus (channel 3) is disabled - txds3fp_11 (transmit ds3 frame pulse input/outp ut - channel 11): if the sts-3/stm-1 telecom bus (channel 3) is disabled and if the ds3/e3 framer block is enabled then this pin will function as either a transmit framing reference input pin or as a transmit framing ref - erence output pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the loop-timing or in the local-timing/ asynchronous framing mode: this pin will function as a frami ng reference output pin. the frame generator block (associated with channel 11) will pulse this output pin "high" for one ds3/e3 bit-period, one period prior to the first bit of a given ds3 or e3 frame being applied to the ds3/e3/ sts1_data_in_11 input pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the local-timing/txds3fp mode: this pin will function as a framing reference input pin. in this mode, the user is expected to pulse this input pin "high" for one ds3 or e3 bit-period, coincident with the firs t bit of a given ds3 or e3 frame, being placed on the ds3/e3/sts1_data_in_11 input pin. the frame generator block (associated with channel 11) will synchro - nize its generation of ds3 or e3 frames to these framing pulses applied to this input pin. n ote : this pin is inactive if the fr ame generator block, associated with channel 11 is by-passed. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 177 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 b22 sts3txa_dp_0 txds3fp_4 txsts1pl_4 i/o ttl/ cmos sts-3/stm-1 transmit telecom bus - parity input pin - channel 0; ds3/e3 frame generator fram ing pulse input/output pin - channel 4: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface for channel 0 has been enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bus - parity input pin: this input pin can be configured to function as one of the following. 1. the even or odd parity value of the bits which are input via the st3txa_d_0[7:0] input pins. 2. the even or odd parity value of the bits which are being input via the sts3txa_d_0[7:0] input and the states of the sts3txa_pl_0 and sts3txa_c1j1_0 input pins. n ote : any one of these configurati on selections can be made by writing the appropriate value into the interface control register - byte 0 register (i ndirect address = 0x00, 0x3b), (direct address = 0x013b). if sts-3/stm-1 telecom bus (channel 0) is disabled - txds3fp_4 (transmit ds3 frame pulse input/outp ut - channel 4): if the sts-3/stm-1 telecom bus (channel 0) is disabled and if the ds3/e3 framer block is enabled then this pin will function as either a transmit framing reference input pin or as a transmit framing ref - erence output pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the loop-timing or in the local-timing/ asynchronous framing mode: this pin will function as a frami ng reference output pin. the frame generator block (associated with channel 4) will pulse this output pin "high" for one ds3/e3 bit-period, one period prior to the first bit of a given ds3 or e3 frame being applied to the ds3/e3/ sts1_data_in_4 input pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the local-timing/txds3fp mode: this pin will function as a framing reference input pin. in this mode, the user is expected to pulse this input pin "high" for one ds3 or e3 bit-period, coincident with the first bit of a given ds3 or e3 frame, being placed on the ds3/e3/sts1_data_in_4 input pin. the frame generator block (associated with channel 4) will synchronize its gen - eration of ds3 or e3 frames to t hese framing pulses applied to this input pin. n ote : this pin is inactive if the frame generator block, associated with channel 4 is by-passed. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 178 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper g23 sts3txa_dp_1 txds3fp_5 txsts1pl_5 i/o ttl/ cmos sts-3/stm-1 transmit telecom bus - parity input pin - channel 1, ds3/e3 frame generator framing pulse input/output pin - channel 5: if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit teleco m bus - parity input pin: this input pin can be configured to function as one of the following. 1. the even or odd parity value of the bits which are input via the st3txa_d_1[7:0] input pins. 2. the even or odd parity value of the bits which are being input via the sts3txa_d_1[7:0] input and the states of the sts3txa_pl_1 and sts3txa_c1j1_1 input pins. n ote : any one of these configurati on selections can be made by writing the appropriate value into the interface control register - byte 1 register (i ndirect address = 0x00, 0x3a), (direct address = 0x013a). if sts-3/stm-1 telecom bus (channel 1) is disabled - txds3fp_5 (transmit ds3 frame pulse input/outp ut - channel 5): if the sts-3/stm-1 telecom bus (channel 1) is disabled and if the ds3/e3 framer block is enabled then this pin will function as either a transmit framing reference input pin or as a transmit framing ref - erence output pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the loop-timing or in the local-timing/ asynchronous framing mode: this pin will function as a frami ng reference output pin. the frame generator block (associated with cha nnel 5) will pulse this output pin "high" for one ds3/e3 bit-period, one period prior to the first bit of a given ds3 or e3 frame being applied to the ds3/e3/ sts1_data_in_5 input pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the local-timing/txds3fp mode: this pin will function as a framing reference input pin. in this mode, the user is expected to pulse this input pin "high" for one ds3 or e3 bit-period, coincident with the firs t bit of a given ds3 or e3 frame, being placed on the ds3/e3/sts1_data_in_5 input pin. the frame generator block (associated with channel 5) will synchronize its gen - eration of ds3 or e3 frames to t hese framing pulses applied to this input pin. n ote : this pin is inactive if the fr ame generator block, associated with channel 5 is by-passed. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 179 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ae24 sts3txa_dp_2 txds3fp_6 txsts1pl_6 i/o ttl/ cmos sts-3/stm-1 transmit telecom bus - parity input pin - channel 2, ds3/e3 frame generator framing pulse input/output pin - channel 6: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface for channel 2 has been enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - parity input pin: this input pin can be configured to function as one of the following. 1. the even or odd parity value of the bits which are input via the st3txa_d_2[7:0] input pins. 2. the even or odd parity value of the bits which are being input via the sts3txa_d_2[7:0] input and the states of the sts3txa_pl_2 and sts3txa_c1j1_2 input pins. n ote : any one of these configurati on selections can be made by writing the appropriate value into the interface control register - byte 2 register (indirect address = 0x00, 0x39), (direct address = 0x0139). if sts-3/stm-1 telecom bus (channel 2) is disabled - txds3fp_6 (transmit ds3 frame pulse input/outp ut - channel 6): if the sts-3/stm-1 telecom bus (channel 2) is disabled and if the ds3/e3 framer block is enabled then this pin will function as either a transmit framing reference input pin or as a transmit framing ref - erence output pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the loop-timing or in the local-timing/ asynchronous framing mode: this pin will function as a frami ng reference output pin. the frame generator block (associated with channel 6) will pulse this output pin "high" for one ds3/e3 bit-period, one period prior to the first bit of a given ds3 or e3 frame being applied to the ds3/e3/ sts1_data_in_6 input pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the local-timing/txds3fp mode: this pin will function as a framing reference input pin. in this mode, the user is expected to pulse this input pin "high" for one ds3 or e3 bit-period, coincident with the first bit of a given ds3 or e3 frame, being placed on the ds3/e3/sts1_data_in_6 input pin. the frame generator block (associated with channel 6) will synchronize its gen - eration of ds3 or e3 frames to t hese framing pulses applied to this input pin. n ote : this pin is inactive if the frame generator block, associated with channel 6 is by-passed. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 180 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ae19 sts3txa_dp_3 txds3fp_7 txsts1pl_7 i/o ttl/ cmos sts-3/stm-1 transmit telecom bus - parity input pin - channel 3; ds3/e3 frame generator fram ing pulse input/output pin - channel 7: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface for channel 3 has been enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit teleco m bus - parity input pin: this input pin can be configured to function as one of the following. 1. the even or odd parity value of the bits which are input via the st3txa_d_3[7:0] input pins. 2. the even or odd parity value of the bits which are being input via the sts3txa_d_3[7:0] input and the states of the sts3txa_pl_3 and sts3txa_c1j1_3 input pins. n ote : any one of these configurati on selections can be made by writing the appropriate value into the interface control register - byte 3 register (indirect address = 0x00, 0x38), (direct address = 0x0138). if sts-3/stm-1 telecom bus (channel 0) is disabled - txds3fp_7 (transmit ds3 frame pulse input/outp ut - channel 7): if the sts-3/stm-1 telecom bus (channel 3) is disabled and if the ds3/e3 framer block is enabled then this pin will function as either a transmit framing reference input pin or as a transmit framing ref - erence output pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the loop-timing or in the local-timing/ asynchronous framing mode: this pin will function as a frami ng reference output pin. the frame generator block (associated with cha nnel 7) will pulse this output pin "high" for one ds3/e3 bit-period, one period prior to the first bit of a given ds3 or e3 frame being applied to the ds3/e3/ sts1_data_in_7 input pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the local-timing/txds3fp mode: this pin will function as a framing reference input pin. in this mode, the user is expected to pulse this input pin "high" for one ds3 or e3 bit-period, coincident with the firs t bit of a given ds3 or e3 frame, being placed on the ds3/e3/sts1_data_in_7 input pin. the frame generator block (associated with channel 7) will synchronize its gen - eration of ds3 or e3 frames to t hese framing pulses applied to this input pin. n ote : this pin is inactive if the fr ame generator block, associated with channel 7 is by-passed. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 181 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 b18 sts3txa_alarm_0 txds3fp_0 txsts1pl_0 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus - alarm indicator input - channel 0; ds3/e3 frame generator framing pulse input/out - put pin - channel 0: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface for channel 0 has been enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bus - alarm indicator input: this input pin pulses "high" coincident to any sts-1 signal (which is carrying the ais-p indicator) being applied to the sts3txa_d_0[7:0] input data bus. n ote : if the sts3txa_alarm_0 input signal pulses "high" for any given sts-1 signal (within the incoming sts-3), then the xrt94l43 will automatically decla re an ais-p for that sts-1 channel. if sts-3/stm-1 telecom bus (channel 0) is disabled - txds3fp_0 (transmit ds3 frame pulse input/outp ut - channel 0): if the sts-3/stm-1 telecom bus (channel 0) is disabled and if the ds3/e3 framer block is enabled then this pin will function as either a transmit framing reference input pin or as a transmit framing ref - erence output pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the loop-timing or in the local-timing/ asynchronous framing mode: this pin will function as a frami ng reference output pin. the frame generator block (associated with channel 0) will pulse this output pin "high" for one ds3/e3 bit-period, one period prior to the first bit of a given ds3 or e3 frame being applied to the ds3/e3/ sts1_data_in_0 input pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the local-timing/txds3fp mode: this pin will function as a framing reference input pin. in this mode, the user is expected to pulse this input pin "high" for one ds3 or e3 bit-period, coincident with the first bit of a given ds3 or e3 frame, being placed on the ds3/e3/sts1_data_in_0 input pin. the frame generator block (associated with channel 0) will synchronize its gen - eration of ds3 or e3 frames to t hese framing pulses applied to this input pin. n ote : this pin is inactive if the frame generator block, associated with channel 0 is by-passed. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 182 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper d25 sts3txa_alarm_1 txds3fp_1 txsts1pl_1 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus - alarm indicator input - channel 1; ds3/e3 frame generator framing pulse input/out - put pin - channel 1: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface for channel 1 has been enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - alarm indicator input: this input pin pulses "high" coincident to any sts-1 signal (which is carrying the ais-p indicator) being applied to the sts3txa_d_1[7:0] input data bus. n ote : if the sts3txa_alarm_1 input signal pulses "high" for any given sts-1 signal (within the incoming sts-3), then the xrt94l43 will automatically decla re an ais-p for that sts-1 channel. if sts-3/stm-1 telecom bus (channel 1) is disabled - txds3fp_1 (transmit ds3 frame pulse input/outp ut - channel 1): if the sts-3/stm-1 telecom bus (channel 1) is disabled and if the ds3/e3 framer block is enabled then this pin will function as either a transmit framing reference input pin or as a transmit framing ref - erence output pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the loop-timing or in the local-timing/ asynchronous framing mode: this pin will function as a frami ng reference output pin. the frame generator block (associated with cha nnel 1) will pulse this output pin "high" for one ds3/e3 bit-period, one period prior to the first bit of a given ds3 or e3 frame being applied to the ds3/e3/ sts1_data_in_1 input pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the local-timing/txds3fp mode: this pin will function as a framing reference input pin. in this mode, the user is expected to pulse this input pin "high" for one ds3 or e3 bit-period, coincident with the firs t bit of a given ds3 or e3 frame, being placed on the ds3/e3/sts1_data_in_1 input pin. the frame generator block (associated with channel 1) will synchronize its gen - eration of ds3 or e3 frames to t hese framing pulses applied to this input pin. n ote : this pin is inactive if the fr ame generator block, associated with channel 1 is by-passed. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 183 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ab26 sts3txa_alarm_2 txds3fp_2 txsts1pl_2 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus - alarm indicator input - channel 2; ds3/e3 frame generator framing pulse input/out - put pin - channel 2: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface for channel 2 has been enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - alarm indicator input: this input pin pulses "high" coincident to any sts-1 signal (which is carrying the ais-p indicator) being applied to the sts3txa_d_2[7:0] input data bus. n ote : if the sts3txa_alarm_2 input signal pulses "high" for any given sts-1 signal (within the incoming sts-3), then the xrt94l43 will automatically decla re an ais-p for that sts-1 channel. if sts-3/stm-1 telecom bus (channel 2) is disabled - txds3fp_2 (transmit ds3 frame pulse input/outp ut - channel 2): if the sts-3/stm-1 telecom bus (channel 2) is disabled and if the ds3/e3 framer block is enabled then this pin will function as either a transmit framing reference input pin or as a transmit framing ref - erence output pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the loop-timing or in the local-timing/ asynchronous framing mode: this pin will function as a frami ng reference output pin. the frame generator block (associated with channel 2) will pulse this output pin "high" for one ds3/e3 bit-period, one period prior to the first bit of a given ds3 or e3 frame being applied to the ds3/e3/ sts1_data_in_2 input pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the local-timing/txds3fp mode: this pin will function as a framing reference input pin. in this mode, the user is expected to pulse this input pin "high" for one ds3 or e3 bit-period, coincident with the first bit of a given ds3 or e3 frame, being placed on the ds3/e3/sts1_data_in_2 input pin. the frame generator block (associated with channel 2) will synchronize its gen - eration of ds3 or e3 frames to t hese framing pulses applied to this input pin. n ote : this pin is inactive if the frame generator block, associated with channel 2 is by-passed. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 184 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper af22 sts3txa_alarm_3 txds3fp_3 txsts1pl_3 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus - alarm indicator input - channel 3; ds3/e3 frame generator framing pulse input/out - put pin - channel 3: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface for channel 3 has been enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus - alarm indicator input: this input pin pulses "high" coincident to any sts-1 signal (which is carrying the ais-p indicator) being applied to the sts3txa_d_3[7:0] input data bus. n ote : if the sts3txa_alarm_3 input signal pulses "high" for any given sts-1 signal (within the incoming sts-3), then the xrt94l43 will automatically decla re an ais-p for that sts-1 channel. if sts-3/stm-1 telecom bus (channel 3) is disabled - txds3fp_3 (transmit ds3 frame pulse input/outp ut - channel 3): if the sts-3/stm-1 telecom bus (channel 3) is disabled and if the ds3/e3 framer block is enabled then this pin will function as either a transmit framing reference input pin or as a transmit framing ref - erence output pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the loop-timing or in the local-timing/ asynchronous framing mode: this pin will function as a frami ng reference output pin. the frame generator block (associated with cha nnel 3) will pulse this output pin "high" for one ds3/e3 bit-period, one period prior to the first bit of a given ds3 or e3 frame being applied to the ds3/e3/ sts1_data_in_3 input pin. if the frame generator (within the ds3/e3 framer block) is con - figured to operate in the local-timing/txds3fp mode: this pin will function as a framing reference input pin. in this mode, the user is expected to pulse this input pin "high" for one ds3 or e3 bit-period, coincident with the firs t bit of a given ds3 or e3 frame, being placed on the ds3/e3/sts1_data_in_3 input pin. the frame generator block (associated with channel 3) will synchronize its gen - eration of ds3 or e3 frames to t hese framing pulses applied to this input pin. n ote : this pin is inactive if the fr ame generator block, associated with channel 3 is by-passed. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 185 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 c15 sts3txa_d_0_0 txsbdata_0 rloop_0 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus - channel 0 - input data bus pin number 0/rloop_0 (general purpose) output pin: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 0: this input pin along with sts3txa_ d_0[7:1] function as the sts-3/ stm-1 transmit (add) telecom bus - input data bus for channel 0. this input pin functions as the lsb (least significant bit) input pin on the transmit (add) telecom bus - input data bus. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_0. the lsb of any byte, which is being input into the sts-3/stm-1 transmit telecom bus - data bus (for channel 0) should be input via this pin. if sts-3/stm-1 telecom bus (chann el 0) is disabled - rloop_0 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropri - ate value into bit 1 (rloop) within the line interface drive register associated with channel 0 (indirect address = 0x1e, 0x80), (direct address = 0x1f80). n ote : for product legacy purposes, this pin is called rloop_0 because one possible application is to tie this output pin to an rloop (remote loop-back) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 186 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper c16 sts3txa_d_0_1 txsbdata_1 req_0 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus - channel 0 - input data bus pin number 0/req_0 (general purpose) output pin: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 1: this input pin along with sts3tx a_d_0[7:2] and sts3txa_d_0_0 function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 0. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - req_0 (general purpose) output pin . this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropri - ate value into bit 5 (reqb) within the line interface drive register associated with channel 0 (indirect address = 0x1e, 0x80), (direct address = 0x1f01). n ote : for product legacy purposes, this pin is called req_0 because one possible application is to tie this output pin to an reqb (receive equalizer by-pass) or reqen (receive equalizer enable) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 187 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 b19 sts3txa_d_0_2 txsbdata_2 ds3/e3/ sts1_data_in_0 i ttl transmit sts-3/stm-1 telecom bus - channel 0 - input data bus pin number 2/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 0: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 2: sts3txa_d_0_2 this input pin along with sts3txa_d_0[7:3] and sts3txa_d_0[1:0] function as the sts-3/stm-1 transmit (add) telecom bus - input data bus for channel 0. the sts-3/stm-1 tele - com bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 0: this input accepts single-rail, recovered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 0). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_0 signal pin number f15. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_0 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 0 (indirect address = 0x1e, 0x01), (direct address = 0x1f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_0 signal upon the rising edge of ds3/e3/ sts1_clk_in_0. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 188 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper b23 sts3txa_d_0_3 txsbdata_3 ds3/e3/ sts1_data_in_4 i ttl transmit sts-3/stm-1 telecom bus - channel 0 - input data bus pin number 3/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 4: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 2: sts3txa_d_0_3: this input pin along with sts3txa_ d_0[7:4] and st s3txa_d_0[2:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 0. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 4: this input accepts single-rail, re covered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 4). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_4 signal pin number a22. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_4 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 4 (indirect address = 0x5e, 0x01), (direct address = 0x5f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_4 signal upon the rising edge of ds3/e3/ sts1_clk_in_4. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 189 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 b25 sts3txa_d_0_4 txsbdata_4 ds3/e3/ sts1_data_in_8 i ttl transmit sts-3/stm-1 telecom bus - channel 0 - input data bus pin number 3/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 4: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 4: sts3txa_d_0_4: this input pin along with sts3txa_ d_0[7:5] and sts3txa_d_0[3:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 0. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 8: this input accepts single-rail, recovered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 8). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_8 signal pin number a24. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_8 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 8 (indirect address = 0x9e, 0x01), (direct address = 0x9f01) to a "1". for sts-1 applications: the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_8 signal upon the rising edge of ds3/e3/ sts1_clk_in_8. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 190 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper f15 sts3txa_d_0_5 txsbdata_5 ds3/e3/ sts1_clk_in_0 i ttl transmit sts-3/stm-1 telecom bus - channel 0 - input data bus pin number 5/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 0: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 5: sts3txa_d_0_5: this input pin along with sts3txa_d_0[7:6] and sts3txa_d_0[4:0] function as the sts-3/stm-1 transmit (add) telecom bus - input data bus for channel 0. the sts-3/stm-1 tele - com bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 0: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 0). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/s ts1_data_in_0 input pin number b19. by default, the data that is appl ied to the ds3/e3/sts1_data_in_0 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_0 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 0 (indirect address = 0x1e, 0x01)," (direct address = 0x1f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_0 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 191 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 a22 sts3txa_d_0_6 txsbdata_6 ds3/e3/ sts1_clk_in_4 i ttl transmit sts-3/stm-1 telecom bus - channel 0 - input data bus pin number 6/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 4: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 6: sts3txa_d_0_6: this input pin along with sts3 txa_d_0_7 and sts3txa_d_0[5:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 0. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 4: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 4). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_4 input pin number b23. by default, the data that is appl ied to the ds3/e3/sts1_data_in_4 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_4 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 4 (indirect address = 0x5e, 0x01), (direct address = 0x5f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_4 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 192 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper a24 sts3txa_d_0_7 txsb_data_7 ds3/e3/ sts1_clk_in_8 i ttl transmit sts-3/stm-1 telecom bus - channel 0 - input data bus pin number 7/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 8: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 7: sts3txa_d_0_7: this input pin along with sts3txa_d_0[6:0] function as the sts-3/ stm-1 transmit (add) telecom bus - input data bus for channel 0. the sts-3/stm-1 telecom bus inte rface will sample and latch this pin upon the falling edge of sts3txa_clk_0. n ote : this input pin functions as the msb (most significant bit) of the transmit (add) telecom bus, for channel 0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 8: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 8). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/s ts1_data_in_8 input pin number b25. by default, the data that is appl ied to the ds3/e3/sts1_data_in_8 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_8 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 8 (indirect address = 0x9e, 0x01), " (direct address = 0x9f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_8 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 193 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 c25 sts3txa_d_1_0 txsbdata_0 rloop_1 i/o ttl transmit sts-3/stm-1 telecom bus - channel 1 - input data bus pin number 0/rloop_1 (general purpose) output pin: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 0: this input pin along with sts3txa_ d_1[7:1] function as the sts-3/ stm-1 transmit (add) telecom bus - input data bus for channel 1. this input pin functions as the lsb (least significant bit) input pin on the transmit (add) telecom bus - input data bus. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_1. the lsb of any byte, which is be ing input into the sts-3/stm-1 transmit telecom bus - data bus (for channel 1) should be input via this pin. if sts-3/stm-1 telecom bus (chann el 1) is disabled - rloop_1 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropri - ate value into bit 1 (rloop) within the line interface drive register associated with channel 1 (indirect address = 0x2e, 0x80), (direct address = 0x2f80). n ote : for product legacy purposes, this pin is called rloop_1 because one possible application is to tie this output pin to an rloop (remote loop-back) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 194 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper b26 sts3txa_d_1_1 txsbdata_1 req_1 i/o ttl transmit sts-3/stm-1 telecom bus - channel 1 - input data bus pin number 1/req_1 (general purpose) output pin: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 1: this input pin along with sts3tx a_d_1[7:2] and sts3txa_d_1_0 function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 1. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - req_1 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropri - ate value into bit 5 (reqb) within the line interface drive register associated with channel 1 (indirect address = 0x2e, 0x80), (direct address = 0x2f80). n ote : for product legacy purposes, this pin is called req_1 because one possible application is to tie this output pin to an reqb (receive equalizer by-pass) or reqen (receive equalizer enable) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 195 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 e26 sts3txa_d_1_2 txsbdata_2 ds3/e3/ sts1_data_in_1 i ttl transmit sts-3/stm-1 telecom bus - channel 1 - input data bus pin number 2/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 1: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 2: sts3txa_d_1_2: this input pin along with sts3txa_d_1[7:3] and sts3txa_d_1[1:0] function as the sts-3/stm-1 transmit (add) telecom bus - input data bus for channel 1. the sts-3/stm-1 tele - com bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 1: this input accepts single-rail, recovered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 1). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_1 signal pin number d26. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_1 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 1 (indirect address = 0x2e, 0x01), (direct address = 0x2f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_1 signal upon the rising edge of ds3/e3/ sts1_clk_in_1. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 196 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper g24 sts3txa_d_1_3 txsbdata_3 ds3/e3/ sts1data_in_5 i ttl transmit sts-3/stm-1 telecom bus - channel 1 - input data bus pin number 3/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 5: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 3: sts3txa_d_1_3: this input pin along with sts3txa_ d_1[7:4] and st s3txa_d_1[2:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 1. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 5: this input accepts single-rail, re covered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 5). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_5 signal pin number f23. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_5 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 5 (indirect address = 0x6e, 0x01), (direct address = 0x6f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_5 signal upon the rising edge of ds3/e3/ sts1_clk_in_5. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 197 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 j24 sts3txa_d_1_4 txsbdata_4 ds3/e3/ sts1_data_in_9 i ttl transmit sts-3/stm-1 telecom bus - channel 1 - input data bus pin number 4/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 9: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 4: sts3txa_d_1_4: this input pin along with sts3txa_d_1[7:5] and sts3txa_d_1[3:0] function as the sts-3/stm-1 transmit (add) telecom bus - input data bus for channel 1. the sts-3/stm-1 tele - com bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 9: this input accepts single-rail, recovered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 9). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_9 signal pin number h23. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_9 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 9 (indirect address = 0xae, 0x01), (direct address = 0xaf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_9 signal upon the rising edge of ds3/e3/ sts1_clk_in_9. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 198 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper d26 sts3txa_d_1_5 ds3/e3/ sts1_clk_in_1 txsbdata_5 i ttl transmit sts-3/stm-1 telecom bus - channel 1 - input data bus pin number 5/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 1: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 5: sts3txa_d_1_5: this input pin along with sts3txa_ d_1[7:6] and st s3txa_d_1[4:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 1. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 1: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 1). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_1 input pin num - ber e26. by default, the data that is appl ied to the ds3/e3/sts1_data_in_1 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_1 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 1 (indirect address = 0x2e, 0x01), (direct address = 0x2f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_1 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 199 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 f23 sts3txa_d_1_6 ds3/e3/ sts1_clk_in_5 txsbdata_6 i ttl transmit sts-3/stm-1 telecom bus - channel 1 - input data bus pin number 6/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 5: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 6: sts3txa_d_1_6: this input pin along with sts3txa_d_1_7 and sts3txa_d_1[5:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 1. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 5: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 5). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_5 input pin num - ber g24. by default, the data that is appl ied to the ds3/e3/sts1_data_in_5 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_5 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 5 (indirect address = 0x6e, 0x01), (direct address = 0x6f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_5 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 200 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper h23 sts3txa_d_1_7 ds3/e3/ sts1_clk_in_9 txsbdata_7 i ttl transmit sts-3/stm-1 telecom bus - channel 1 - input data bus pin number 7/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 9: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 7: sts3txa_d_1_7: this input pin along with sts3txa_d_1[6:0] function as the sts-3/ stm-1 transmit (add) telecom bus - input data bus for channel 1. the sts-3/stm-1 telecom bus inte rface will sample and latch this pin upon the falling edge of sts3txa_clk_1. n ote : this input pin functions as the msb (most significant bit) of the transmit (add) telecom bus, for channel 1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 9: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 9). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_9 input pin num - ber j24. by default, the data that is appl ied to the ds3/e3/sts1_data_in_9 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_9 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 9 (indirect address = 0xae, 0x01), " (direct address = 0xaf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_9 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 201 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ad26 sts3txa_d_2_0 rloop_2 txsbdata_0 i/o ttl transmit sts-3/stm-1 telecom bus - channel 2 - input data bus pin number 0/rloop_2 (general purpose) output pin: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 0: this input pin along with sts3txa_ d_2[7:1] function as the sts-3/ stm-1 transmit (add) telecom bus - input data bus for channel 2. this input pin functions as the lsb (least significant bit) input pin on the transmit (add) telecom bus - input data bus. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_2. the lsb of any byte, which is be ing input into the sts-3/stm-1 transmit telecom bus - data bus (for channel 2) should be input via this pin. if sts-3/stm-1 telecom bus (chann el 2) is disabled - rloop_2 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropri - ate value into bit 1 (rloop) within the line interface drive register associated with channel 2 (indirect address = 0x3e, 0x80), (direct address = 0x3f80). n ote : for product legacy purposes, this pin is called rloop_2 because one possible application is to tie this output pin to an rloop (remote loop-back) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 202 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ae26 sts3txa_d_2_1 req_2 txsbdata_1 i/o ttl transmit sts-3/stm-1 telecom bus - channel 2 - input data bus pin number 1/req_2 (general purpose) output pin: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 1: this input pin along with sts3tx a_d_2[7:2] and sts3txa_d_2_0 function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 2. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - req_2 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropri - ate value into bit 5 (reqb) within the line interface drive register associated with channel 2 (indirect address = 0x3e, 0x80), (direct address = 0x3f80). n ote : for product legacy purposes, this pin is called req_2 because one possible application is to tie this output pin to an reqb (receive equalizer by-pass) or reqen (receive equalizer enable) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 203 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 v24 sts3txa_d_2_2 ds3/e3/ sts1_data_in_2 txsbdata_2 i ttl transmit sts-3/stm-1 telecom bus - channel 2 - input data bus pin number 2/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 2: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 2: sts3txa_d_2_2: this input pin along with sts3txa_d_2[7:3] and sts3txa_d_2[1:0] function as the sts-3/stm-1 transmit (add) telecom bus - input data bus for channel 2. the sts-3/stm-1 tele - com bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 2: this input accepts single-rail, recovered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 2). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_2 signal pin number v25. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_2 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 2 (indirect address = 0x3e, 0x01), (direct address = 0x3f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_2 signal upon the rising edge of ds3/e3/ sts1_clk_in_2. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 204 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ad24 sts3txa_d_2_3 ds3/e3/ sts1_data_in_6 txsbdata_3 i ttl transmit sts-3/stm-1 telecom bus - channel 2 - input data bus pin number 3/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 6: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 3: sts3txa_d_2_3: this input pin along with sts3txa_ d_2[7:4] and st s3txa_d_2[2:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 2. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 6: this input accepts single-rail, re covered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 6). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_6 signal pin number y22. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_6 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 6 (indirect address = 0x7e, 0x01), (direct address = 0x7f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_6 signal upon the rising edge of ds3/e3/ sts1_clk_in_6. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 205 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 af25 sts3txa_d_2_4 ds3/e3/ sts1_data_in_10 txsbdata_4 i ttl transmit sts-3/stm-1 telecom bus - channel 2 - input data bus pin number 4/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 10: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 4: sts3txa_d_2_4: this input pin along with sts3txa_ d_2[7:5] and sts3txa_d_2[3:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 2. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 line interface data input - channel 10: this input accepts single-rail, recovered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 10). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/ sts1_clk_in_10 signal pin number ab22. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_10 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 10 (indirect address = 0xbe, 0x01), (direct address = 0xbf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_10 signal upon the rising edge of ds3/e3/ sts1_clk_in_10. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 206 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper v25 sts3txa_d_2_5 ds3/e3/ sts1_clk_in_2 txsbdata_5 i ttl transmit sts-3/stm-1 telecom bus - channel 2 - input data bus pin number 5/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 2: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 5: sts3txa_d_2_5: this input pin along with sts3txa_ d_2[7:6] and st s3txa_d_2[4:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 2. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 2: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 2). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_2 input pin num - ber v24. by default, the data that is appl ied to the ds3/e3/sts1_data_in_2 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_2 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 2 (indirect address = 0x3e, 0x01), (direct address = 0x3f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_2 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 207 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 y22 sts3txa_d_2_6 ds3/e3/ sts1_clk_in_6 txsbdata_6 i ttl transmit sts-3/stm-1 telecom bus - channel 2 - input data bus pin number 6/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 6: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 6: sts3txa_d_2_6: this input pin along with sts3txa_d_2_7 and sts3txa_d_2[5:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 2. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 6: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 6). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_6 input pin num - ber ad24. by default, the data that is appl ied to the ds3/e3/sts1_data_in_6 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_6 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 6 (indirect address = 0x7e, 0x01), (direct address = 0x7f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_6 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 208 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ab22 sts3txa_d_2_7 ds3/e3/ sts1_clk_in_10 txsbdata_7 i ttl transmit sts-3/stm-1 telecom bus - channel 2 - input data bus pin number 7/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 10: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 7: sts3txa_d_2_7: this input pin along with sts3txa_ d_2[6:0] function as the sts-3/ stm-1 transmit (add) telecom bus - input data bus for channel 2. the sts-3/stm-1 telecom bus inte rface will sample and latch this pin upon the falling edge of sts3txa_clk_2. n ote : this input pin functions as the msb (most significant bit) of the transmit (add) telecom bus, for channel 2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 10: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 10). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_10 input pin number af25. by default, the data that is applied to the ds3/e3/ sts1_data_in_10 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_10 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 10 (indirect address = 0xbe, 0x01), (direct address = 0xbf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_10 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 209 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ac18 sts3txa_d_3_0 rloop_3 txsbdata_0 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus - channel 3 - input data bus pin number 0/rloop_3 general purpose) output pin: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 0: this input pin along with sts3txa_ d_3[7:1] function as the sts-3/ stm-1 transmit (add) telecom bus - input data bus for channel 3. this input pin functions as the lsb (least significant bit) input pin on the transmit (add) telecom bus - input data bus. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_3. the lsb of any byte, which is being input into the sts-3/stm-1 transmit telecom bus - data bus (for channel 3) should be input via this pin. if sts-3/stm-1 telecom bus (chann el 3) is disabled - rloop_3 (general purpose) output pin. this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropri - ate value into bit 1 (rloop) within the line interface drive register associated with channel 3 (indirect address = 0x4e, 0x80), (direct address = 0x4f80). n ote : for product legacy purposes, this pin is called rloop_3 because one possible application is to tie this output pin to an rloop (remote loop-back) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 210 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ab18 sts3txa_d_3_1 req_3 txsbdata_1 i/o ttl/ cmos transmit sts-3/stm-1 telecom bus - channel 3 - input data bus pin number 1/req_3 (general purpose) output pin: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 1: this input pin along with sts3tx a_d_3[7:2] and sts3txa_d_3_0 function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 3. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - req_3 (general purpose) output pin. this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropri - ate value into bit 5 (reqb) within the line interface drive register associated with channel 3 (indirect address = 0x4e, 0x80), (direct address = 0x4f80). n ote : for product legacy purposes, this pin is called req_3 because one possible application is to tie this output pin to an reqb (receive equalizer by-pass) or reqen (receive equalizer enable) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 211 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 aa20 sts3txa_d_3_2 ds3/e3/ sts1_data_in_3 txsbdata_2 i ttl transmit sts-3/stm-1 telecom bus - channel 3 - input data bus pin number 2/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 3: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 2: sts3txa_d_3_2: this input pin along with sts3txa_ d_3[7:3] and sts3txa_d_3[1:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 3. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 3: this input accepts single-rail, recovered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 3). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_3 signal pin number ad22. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_3 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 3 (indirect address = 0x4e, 0x01), (direct address = 0x4f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_3 signal upon the rising edge of ds3/e3/ sts1_clk_in_3. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 212 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ab19 sts3txa_d_3_3 ds3/e3/ sts1_data_in_7 txsbdata_3 i ttl transmit sts-3/stm-1 telecom bus - channel 3 - input data bus pin number 3/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 7: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 3: sts3txa_d_3_3: this input pin along with sts3txa_d_3[7:4] and sts3txa_d_3[2:0] function as the sts-3/stm-1 transmit (add) telecom bus - input data bus for channel 3. the sts-3/stm-1 tele - com bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 7: this input accepts single-rail, re covered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 7). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/sts1_clk_in_7 signal pin number aa19. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_7 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 7 (indirect address = 0x8e, 0x01), (direct address = 0x8f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_7 signal upon the rising edge of ds3/e3/ sts1_clk_in_7. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 213 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ad16 sts3txa_d_3_4 ds3/e3/ sts1_data_in_11 txsbdata_4 i ttl transmit sts-3/stm-1 telecom bus - channel 3 - input data bus pin number 4/ds3/e3 framer or receive sts-1 toh processor block line interface input pin - channel 11 (ds3/e3/ sts1_data_in_11): the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 4: sts3txa_d_3_4: this input pin along with sts3txa_d_3[7:5] and sts3txa_d_3[3:0] function as the sts-3/stm-1 transmit (add) telecom bus - input data bus for channel 3. the sts-3/stm-1 tele - com bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_data_in - ds3/e3/sts-1 li ne interface data input - chan - nel 11: this input accepts single-rail, recovered ds3, e3 or sts-1 data (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rpos output of the ds3/e3/s ts-1 liu ic (corresponding to channel 11). by default, the data that is applied to this input pin will be latched into the xrt94l43 upon the falling edge of the ds3/e3/ sts1_clk_in_11 signal pin number ab16. for ds3/e3 applications the xrt94l43 can be configured to latch this input signal upon the rising edge of the ds3/e3/sts1_clk_in_11 signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 11 (indirect address = 0xce, 0x01), (direct address = 0xcf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_11 signal upon the rising edge of ds3/e3/ sts1_clk_in_11. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 214 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ad22 sts3txa_d_3_5 ds3/e3/ sts1_clk_in_3 txsbdata_5 i ttl transmit sts-3/stm-1 telecom bus - channel 3 - input data bus pin number 5/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 3: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 5: sts3txa_d_3_5: this input pin along with sts3txa_d_3[7:6] and sts3txa_d_3[4:0] function as the sts-3/stm-1 transmit (add) telecom bus - input data bus for channel 3. the sts-3/stm-1 tele - com bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 3: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 3). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_3 input pin num - ber aa20. by default, the data that is appl ied to the ds3/e3/sts1_data_in_3 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_3 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 3 (indirect address = 0x4e, 0x01), (direct address = 0x4f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_3 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 215 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 aa19 sts3txa_d_3_6 ds3/e3/ sts1_clk_in_7 txsbdata_6 i ttl transmit sts-3/stm-1 telecom bus - channel 3 - input data bus pin number 6/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 7: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 6: sts3txa_d_3_6: this input pin along with sts3 txa_d_3_7 and sts3txa_d_3[5:0] function as the sts-3/stm-1 tran smit (add) telecom bus - input data bus for channel 3. the sts-3/stm-1 telecom bus interface will sample and latch this pin upon the falling edge of sts3txa_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 7: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 7). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/e3/sts1_data_in_7 input pin num - ber ab19. by default, the data that is appl ied to the ds3/e3/sts1_data_in_7 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_7 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 7 (indirect address = 0x8e, 0x01), (direct address = 0x8f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_7 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 216 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ab16 sts3txa_d_3_7 ds3/e3/ sts1_clk_in_11 txsbdata_7 i ttl transmit sts-3/stm-1 telecom bus - channel 3 - input data bus pin number 7/ds3/e3 framer or receive sts-1 toh processor block line interface clock input pin - channel 11: the function of this pin depends upon whether or not thests-3/stm- 1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 transmit telecom bus - input data bus pin num - ber 7: sts3txa_d_3_7: this input pin along with sts3txa_d_3[6:0] function as the sts-3/ stm-1 transmit (add) telecom bus - input data bus for channel 3. the sts-3/stm-1 telecom bus inte rface will sample and latch this pin upon the falling edge of sts3txa_clk_3. n ote : this input pin functions as the msb (most significant bit) of the transmit (add) telecom bus, for channel 3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/e3/ sts1_clk_in - ds3/e3/sts-1 line interface clock input - chan - nel 11: this input accepts a recovered ds3, e3 or sts-1 clock signal (from a ds3/e3/sts-1 liu ic). this input pin should be connected to the rclk output of the ds3/e3/sts-1 liu ic (corresponding to channel 11). the xrt94l43 uses this clock signal to sample and latch the data that is applied to the ds3/ e3/sts1_data_in_11 input pin num - ber ad16. by default, the data that is applie d to the ds3/e3/sts1_data_in_11 input pin will be latched into the xrt94l43 upon the falling edge of this clock signal. for ds3/e3 applications the xrt94l43 can be configured to latch the ds3/e3/ sts1_data_in_11 signal upon the rising edge of this clock signal by setting bit 1 (ds3/e3/sts1_clk_in invert), within the i/o control register - channel 11 (indirect address = 0xce, 0x01), (direct address = 0xcf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to sample the ds3/e3/ sts1_data_in_11 signal upon the rising edge of this clock signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 217 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ab25 txrefclk sse_pos o cmos transmit sts-3/stm-1 telecom bus reference clock output pin/slow-speed interface - egress - positive data i/o: the exact function of this pin depends upon whether or not thests- 3/stm-1 telecom bus is enabled, and whether the slow-speed interface is enabled. transmit sts-3/stm-1 telecom bus reference clock output pin: this pin generates a 19.44mhz clock signal that is ultimately derived from the clock synthesizer block (within the xrt94l43 device). if the user configures the sts-3/ stm-1 telecom bus interface to operate in the "re-phase off" mode, then the device (or entity) that is transmitting sts-3/stm-1 data (to the transmit sts-3/stm-1 telecom bus interface) must synch ronizes its data transmission to this output signal. the user is not required to use th is signal if the sts-3/stm-1 tele - com bus interface has been configured to operate in the "re-phase on" mode. sse_pos (slow-speed interface - egress - port is enabled): if the slow-speed interface - egress (sse) port is enabled, then this pin will function as either the sse_pos output pin or the sse_pos input pin.if the user configures the sse port to operate in the "insert" mode, then the sse port will be configured to replace any "user- selected" egress ds3/e3 or st s-1 data-stream (within the xrt94l43 device) with the data that is applied to the sse_pos and sse_neg input pins. more specifically , in the "insert" mode, this pin will function as the "sse_pos" input pin. in this case, the sse port will sample and latch the contents of the input pin (along with the sse_neg, in a dual-rail manner) upon the falling edge of the sse_clk input clock signal. if the user configures the sse port to operate in the "extract" mode, then the sse port will output any "user-selected" egress ds3/e3 or sts-1 signal (within the xrt94l43 device) via this output port. more specifically, in the "extract mode" this pin will function as the "sse_pos" output pin. in this ca se, the sse port wi ll output data via this pin, along with the sse_pos output pin (in a dual-rail manner) upon the rising edge of the sse_clk output signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 218 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper aa24 txsbfp_out ssi_neg o cmos transmit sts-3/stm-1 telecom bus framing pulse output pin: this pin generates a pulse at an 8khz rate. this signal is ultimately derived from the clock synthesizer block (within the xrt94l43). if the sts-3/stm-1 telecom bus interf ace is configured to operate in the "re-phase off" mode, then th e devices (or entities) that are transmitting sts-3/stm-1 data (to the transmit sts-3/stm-1 tele - com bus interface) must synchronize their sts-3/stm-1 frame transmission to this output signal. in the re-phase off mode, each device or entity must align their sts-3/stm-1 frame transmission to this signal, in order to insure that all four transmit sts-3/stm-1 telecom bus interfaces are pre - sented with toh data simultaneously. transmit sts-3/stm-1 telecom bus framing pulse output pin/ slow-speed interface - ingress - negative data i/o: the exact function of this pin depends upon whether or not thests- 3/stm-1 telecom bus is enabled and whether the slow-speed inter - face is enabled. transmit sts-3/stm-1 telecom bus framing pulse output pin: this pin generates a pulse at an 8khz rate. this signal is ultimately derived from the clock synthesizer block (within the xrt94l43). if the user configures the sts-3/ stm-1 telecom bus interface to operate in the "re-phase off" mode, then the devices (or entities) that is transmitting sts-3/stm-1 data (to the transmit sts-3/stm-1 telecom bus interface) must syn chronize its sts-3/stm-1 frame transmission to this output signal. in the re-phase off mode, each device or entity must align their sts-3/stm-1 frame transmission to this signal, in order to insure that all four transmit sts-3/stm-1 telecom bus interfaces are pre - sented with toh data simultaneously. ssi_neg (slow-speed interface - ingress port is enabled): if the slow-speed interface - ingress (ssi) port is enabled, then this pin will function as either the ssi_neg output pin or the ssi_neg input pin. if the user configures the ssi port to operate in the "insert" mode, then the ssi port will be configured to replace any "user-selected" ingress ds3/e3 or sts-1 data-stream (within the xrt94l43 device) with the data that is applied to the ssi_pos and ssi_neg input pins. more specifically, in the "insert" mode, this pin will function as the ssi_neg input pin. in this case, the ssi port will sample and latch the contents of this input pin (along with the ssi_pos input pin, in a dual-rail manner) upon the falling edge of the ssi_clk input clock signal. if the user configures the ssi port to operate in the "extract" mode, then the ssi port will output any "u ser-selected" ingress ds3/e3 or sts-1 signal (within the xrt94l43 device) via this output port. more specifically, in the "extract mode" this pin will function as the "ssi_neg" output pin. in this ca se, the ssi port will output data via this pin, along with the ssi_pos output pin (in a dual-rail manner) upon the rising edge of the ssi_clk output signal. sts-3/stm-1 telecom bus interface - transmit direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 219 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 rxsts-1 toh/poh interface p in # s ignal n ame i/o s ignal t ype d escription a14 f20 k25 ad18 e16 h22 aa25 ac15 e19 k22 ad23 aa12 rxsts1ohsel_0 rxsts1ohsel_1 rxsts1ohsel_2 rxsts1ohsel_3 rxsts1ohsel_4 rxsts1ohsel_5 rxsts1ohsel_6 rxsts1ohsel_7 rxsts1ohsel_8 rxsts1ohsel_9 rxsts1ohsel_10 rxsts1ohsel_11 o cmos receive sts-1 toh and poh output port - poh data indicator: these output pins, along with rxsts1ohclk_n, rxsts1ohframe_n and rxsts1oh_n function as the receive sts-1 toh and poh output port. these output pins indicate whether poh or toh data is being output via the rxsts1oh_n output pins. these output pins will toggle "hig h" coincident with the poh data as it is being output via the rxsts1 oh_n output pins. conversely, these output pins will toggle "low " coincident with the toh data as it is being output via the rxsts1oh_n output pins. n ote : these output pins are updat ed upon the falling edge of rxsts1ohclk_n. as a consequence, external circuitry, receiving this data, should sample this data upon the rising edge of rxsts1ohclk_n. d11 g22 u23 ad20 b15 j21 aa26 af15 e17 k23 af26 ad11 rxsts1oh_0 rxsts1oh_1 rxsts1oh_2 rxsts1oh_3 rxsts1oh_4 rxsts1oh_5 rxsts1oh_6 rxsts1oh_7 rxsts1oh_8 rxsts1oh_9 rxsts1oh_10 rxsts1oh_11 o cmos receive sts-1 toh and poh output port - output pin: these output pins, along with rxsts1ohsel_n, rxsts1ohclk_n and rxsts1ohframe_n function as the receive sts-1 toh and poh output port. each bit, within the toh and poh bytes (within the incoming sts-1 data stream) is updated upon the falling edge of rxsts1ohclk_n. as a consequence, external circuitry receiving this data, should sam - ple this data upon the rising edge of rxsts1ohclk_n. n otes : 1. the external circuitry can determine whether or not it is receiving poh or toh data via this output pin. the rxsts1ohsel_n output pin will be "high" anytime poh data is being output via these output pins. conversely, the rxsts1ohsel_n output pin will be "low" anytime toh data is being output via these output pins. 2. toh and poh data, associated with receive sts-1 toh and poh processor block - channel 0 will be output via the rxsts1oh_0, and so on.
xrt94l43 220 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper f12 f22 t24 ae20 a18 h21 ab24 ae16 e18 k26 aa23 af10 rxsts1ohclk_0 rxsts1ohclk_1 rxsts1ohclk_2 rxsts1ohclk_3 rxsts1ohclk_4 rxsts1ohclk_5 rxsts1ohclk_6 rxsts1ohclk_7 rxsts1ohclk_8 rxsts1ohclk_9 rxsts1ohclk_10 rxsts1ohclk_11 o cmos receive sts-1 toh and poh output port - clock output signal: these output pins, along with rxsts1oh_n, rxsts1ohframe_n, and rxsts1ohsel_n function as the receive sts-1 toh and poh output port. these output pins function as the clock output signals for the receive sts-1 toh and poh output port. the rxsts1oh_n, rxsts1frame_n and rxsts1ohsel_n output pins are updated upon the falling edge of this clock signal. d12 e22 u26 af18 b17 j22 w22 af12 f19 k24 af23 ad10 rxsts1ohframe_0 rxsts1ohframe_1 rxsts1ohframe_2 rxsts1ohframe_3 rxsts1ohframe_4 rxsts1ohframe_5 rxsts1ohframe_6 rxsts1ohframe_7 rxsts1ohframe_8 rxsts1ohframe_9 rxsts1ohframe_1 0 rxsts1ohframe_11 o cmos receive sts-1 toh and poh output port - frame boundary indicator: these output pins, along with rxsts1oh_n, rxsts1ohsel_n and rxsts1ohclk_n function as the receive sts-1 toh and poh output port. these output pins will pulse "high" coincident with either of the fol - lowing events. 1. when the very first toh byte (a1), of a given sts-1 frame, is being output via the corresponding rxsts1oh_n output pin. 2. when the very first poh byte (j1), of a given sts-1 frame, is being output via the corresponding rxsts1oh_n output pin. n ote : the external circuitry can det ermine whether these output pins are pulsing "high" for the first toh or poh byte by checking the state of the corresponding rxsts1ohsel_n output pin. rxsts-1 toh/poh interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 221 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2
xrt94l43 222 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper sts-3/stm-1 telecom bus interface - receive direction p in # s ignal n ame i/o s ignal t ype d escription a20 sts3rxd_clk_0 rxsbclklloop_0 o cmos receive sts-3/stm-1 telecom bus clock output - channel 0; lloop_0 (general purpose) output pin: the function of this input pin depends upon whether or not thests-3/stm-1 telecom bus in terface associated with chan - nel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 receive telecom bus clock output - chan - nel 0; sts3rxd_clk_0: all signals, which is output via the receive telecom bus - channel 0 is clocked out upon the rising edge of this clock sig - nal. this includes the following signals. ? sts3rxd_d_0[7:0] ? sts3rxd_alarm_0 ? sts3rxd_dp_0 ? sts3rxd_pl_0 ? sts3rxd_c1j1_0 this clock signal will operate at 19.44mhz. if sts-3/stm-1 telecom bus (channel 0) is disabled - lloop_0 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 0 (lloop) within the line interface drive register associated with channel 0 (indirect address = 0x1e, 0x80), (direct address = 0x1f80). n ote : for product legacy purposes, this pin is called lloop_0 because one possible application is to tie this output pin to an lloop (local loop-back) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/ sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose.
xrt94l43 223 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 d23 sts3rxd_clk_1 rxsbclklloop_1 o cmos receive sts-3/stm-1 telecom bus clock output - channel 1; lloop_1 (general purpose) output pin: the function of this input pin depends upon whether or not thests-3/stm-1 telecom bus interface associated with chan - nel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 receive telecom bus clock output - chan - nel 1; sts3rxd_clk_1: all signals, which is output via the receive telecom bus - channel 1 is clocked out upon the rising edge of this clock sig - nal. this includes the following signals. ? sts3rxd_d_1[7:0] ? sts3rxd_alarm_1 ? sts3rxd_dp_1 ? sts3rxd_pl_1 ? sts3rxd_c1j1_1 this clock signal will operate at 19.44mhz. if sts-3/stm-1 telecom bus (channel 1) is disabled - lloop_1 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 0 (lloop) within the line interface drive register associated with channel 1 (indirect address = 0x2e, 0x80), (direct address = 0x2f80). n ote : for product legacy purposes, this pin is called lloop_1 because one possible application is to tie this output pin to an lloop (local loop-back) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/ sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 224 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper w23 sts3rxd_clk_2 rxsbclklloop_2 o cmos receive sts-3/stm-1 telecom bus clock output - channel 2; lloop_2 (general purpose) output pin: the function of this input pin depends upon whether or not thests-3/stm-1 telecom bus in terface associated with chan - nel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 receive telecom bus clock output - chan - nel 2; sts3rxd_clk_2: all signals, which is output via the receive telecom bus - channel 2 is clocked out upon the rising edge of this clock sig - nal. this includes the following signals. ? sts3rxd_d_2[7:0] ? sts3rxd_alarm_2 ? sts3rxd_dp_2 ? sts3rxd_pl_2 ? sts3rxd_c1j1_2 this clock signal will operate at 19.44mhz. if sts-3/stm-1 telecom bus (channel 2) is disabled - lloop_2 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 0 (lloop) within the line interface drive register associated with channel 2 (indirect address = 0x3e, 0x80), (direct address = 0x3f80). n ote : for product legacy purposes, this pin is called lloop_2 because one possible application is to tie this output pin to an lloop (local loop-back) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/ sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 225 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 af20 sts3rxd_clk_3 rxsbclklloop_3 o cmos receive sts-3/stm-1 telecom bus clock output - channel 3; lloop_3 (general purpose) output pin: the function of this input pin depends upon whether or not thests-3/stm-1 telecom bus interface associated with chan - nel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 receive telecom bus clock output - chan - nel 3; sts3rxd_clk_3: all signals, which is output via the receive telecom bus - channel 3 is clocked out upon the rising edge of this clock sig - nal. this includes the following signals. ? sts3rxd_d_3[7:0] ? sts3rxd_alarm_3 ? sts3rxd_dp_3 ? sts3rxd_pl_3 ? sts3rxd_c1j1_3 this clock signal will operate at 19.44mhz. if sts-3/stm-1 telecom bus (channel 3) is disabled - lloop_3 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 0 (lloop) within the line interface drive register associated with channel 3 (indirect address = 0x4e, 0x80), (direct address = 0x4f80). n ote : for product legacy purposes, this pin is called lloop_3 because one possible application is to tie this output pin to an lloop (local loop-back) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/ sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 226 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper a21 sts3rxd_pl_0 taos_0 o cmos sts-3/stm-1 receive (drop) telecom bus - payload indi - cator output signal - channel 0/taos_0 (general purpose) output pin - channel 0: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus inte rface block asso ciated with channel 0 has been enabled or disabled. if the sts-3/stm-1 telecom bus interface (associated with channel 0) is enabled - sts-3/sts-1 receive (drop) tele - com bus - payload indicator output - sts3rxd_pl_0: this output pin indicates whet her or not transport overhead bytes are being output via the sts3rxd_d_0[7:0] output pins. this output pin is pulled "low" for the duration that the sts-3/ stm-1 receive telecom bus is transmitting a transport over - head byte via the sts3rxd_d_0[7:0] output pins. conversely, this output pin is pulled "high" for the duration that the sts-3/stm-1 receive tele com bus is transmitting some - thing other than a transport overhead byte via the sts3rxd_d_0[7:0] output pins. if the sts-3/stm-1 telecom bus interface (associated with channel 0) is disabled - taos_0 (general purpose) output pin - channel 0: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 4 (taos) within the line interface drive register associated with channel 0 (indirect address = 0x1e, 0x80), (direct address = 0x1f80). n ote : for product legacy purposes, this pin is called taos_0 because one possible application is to tie this output pin to an taos (transmit all ones) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 227 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 d24 sts3rxd_pl_1 taos_1 o cmos sts-3/stm-1 receive (drop) telecom bus - payload indi - cator output signal - channel 1/taos_1 (general purpose) output pin - channel 1: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus inte rface block associated with channel 1 has been enabled or disabled. if the sts-3/stm-1 telecom bus interface (associated with channel 1) is enabled - sts-3/sts-1 receive (drop) tele - com bus - payload indicator output - sts3rxd_pl_1: this output pin indicates whet her or not transport overhead bytes are being output via the sts3rxd_d_1[7:0] output pins. this output pin is pulled "low" for the duration that the sts-3/ stm-1 receive telecom bus is transmitting a transport over - head byte via the sts3rxd_d_1[7:0] output pins. conversely, this output pin is pulled "high" for the duration that the sts-3/stm-1 receive tele com bus is transmitting some - thing other than a transport overhead byte via the sts3rxd_d_1[7:0] output pins. if the sts-3/stm-1 telecom bus interface (associated with channel 1) is disabled - taos_1 (general purpose) output pin - channel 1: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 4 (taos) within the line interface drive register associated with channel 1 (indirect address = 0x2e, 0x80), (direct address = 0x2f80). n ote : for product legacy purposes, this pin is called taos_1 because one possible application is to tie this output pin to an taos (transmit all ones) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 228 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper v23 sts3rxd_pl_2 taos_2 o cmos sts-3/stm-1 receive (drop) telecom bus - payload indi - cator output signal - channel 2/taos_2 (general purpose) output pin - channel 2: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus inte rface block asso ciated with channel 2 has been enabled or disabled. if the sts-3/stm-1 telecom bus interface (associated with channel 2) is enabled - sts-3/sts-1 receive (drop) tele - com bus - payload indicator output - sts3rxd_pl_2: this output pin indicates whet her or not transport overhead bytes are being output via the sts3rxd_d_2[7:0] output pins. this output pin is pulled "low" for the duration that the sts-3/ stm-1 receive telecom bus is transmitting a transport over - head byte via the sts3rxd_d_2[7:0] output pins. conversely, this output pin is pulled "high" for the duration that the sts-3/stm-1 receive tele com bus is transmitting some - thing other than a transport overhead byte via the sts3rxd_d_2[7:0] output pins. if the sts-3/stm-1 telecom bus interface (associated with channel 2) is disabled - taos_2 (general purpose) output pin - channel 2: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 4 (taos) within the line interface drive register associated with channel 2 (indirect address = 0x3e, 0x80), (direct address = 0x3f80). n ote : for product legacy purposes, this pin is called taos_2 because one possible application is to tie this output pin to an taos (transmit all ones) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 229 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 af21 sts3rxd_pl_3 taos_3 o cmos sts-3/stm-1 receive (drop) telecom bus - payload indi - cator output signal - channel 3/taos_3 (general purpose) output pin - channel 3: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus inte rface block associated with channel 3 has been enabled or disabled. if the sts-3/stm-1 telecom bus interface (associated with channel 3) is enabled - sts-3/sts-1 receive (drop) tele - com bus - payload indicator output - sts3rxd_pl_3: this output pin indicates whet her or not transport overhead bytes are being output via the sts3rxd_d_3[7:0] output pins. this output pin is pulled "low" for the duration that the sts-3/ stm-1 receive telecom bus is transmitting a transport over - head byte via the sts3rxd_d_3[7:0] output pins. conversely, this output pin is pulled "high" for the duration that the sts-3/stm-1 receive tele com bus is transmitting some - thing other than a transport overhead byte via the sts3rxd_d_3[7:0] output pins. if the sts-3/stm-1 telecom bus interface (associated with channel 3) is disabled - taos_3 (general purpose) output pin - channel 3: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 4 (taos) within the line interface drive register associated with channel 3 (indirect address = 0x4e, 0x80), (direct address = 0x4f80) . n ote : for product legacy purposes, this pin is called taos_3 because one possible application is to tie this output pin to an taos (transmit all ones) input pin from one of exar's xrt73l0x/xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 230 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper c23 sts3rxd_c1j1_0 rxds3fp_8 txsts1fp_8 rxsbframe_0 o cmos sts-3/stm-1 receive telecom bus - c1/j1 byte phase indicator output signal - channel 0; ds3/e3 frame syn - chronizer framing pulse output pin - channel 8: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface for channel 0 has been enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 receive telecom bus - c1/j1 byte phase indicator output signal: this output pin pulses "high" under the following two condi - tions. 1. whenever the c1 byte is being output via the sts3rxd_d_0[7:0] output, and 2. whenever the j1 byte is being output via the sts3rxd_d_0[7:0] output.1: n otes : 1. the sts-3/stm-1 receiv e (drop) telecom bus (associated with channel 0) will indicate that it is transmitting the c1 byte (via the sts3rxd_d_0[7:0] output pins), by pulsing this output pin "high" (for one period of sts3rxd_clk_0) and keeping the sts3rxd_pl_0 output pin pulled "low". 2. the sts-3/stm-1 receiv e (drop) telecom bus (associated with channel 0) will indicate that it is transmitting the j1 byte (via the sts3rxd_d_0[7:0] output pins), by pulsing this output pin "high" (for one period of sts3rxd_clk_0) while the sts3txd_pl_0 output pin is pulled "high". if sts-3/stm-1 telecom bus (channel 0) is disabled - rxds3fp_8 (receive ds3 frame pulse input/output - channel 8): if the sts-3/stm-1 telecom bus (channel 0) is disabled and if the ds3/e3 framer block is enabled then this pin will function as the receiving framing referenc e output pin. in this mode, the frame synchronizer block (associated with channel 8) will pulse this output pin "high" for one ds3/e3 bit-period, coinci - dent with the first bit (within a given ds3 or e3 frame) being output via the ds3/e3/sts1_data_out_8 output pin. n ote : this pin is inactive if the frame synchronizer block, associated with channel 8 is by-passed. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 231 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 j25 sts3rxd_c1j1_1 rxds3fp_9 txsts1fp_9 rxsbframe_1 o cmos sts-3/stm-1 receive telecom bus - c1/j1 byte phase indicator output signal - channel 1; ds3/e3 frame syn - chronizer framing pulse output pin - channel 9: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface for channel 1 has been enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 receive telecom bus - c1/j1 byte phase indicator output signal: this output pin pulses "high" under the following two condi - tions. 1. whenever the c1 byte is being output via the sts3rxd_d_1[7:0] output. 2. whenever the j1 byte is being output via the sts3rxd_d_1[7:0] output. n otes : 1. the sts-3/stm-1 receiv e (drop) telecom bus (associated with channel 1) will indicate that it is transmitting the c1 byte (via the sts3rxd_d_1[7:0] output pins), by pulsing this output pin "high" (for one period of sts3rxd_clk_1) and keeping the sts3rxd_pl_1 output pin pulled "low". 2. the sts-3/stm-1 receiv e (drop) telecom bus (associated with channel 1) will indicate that it is transmitting the j1 byte (via the sts3rxd_d_1[7:0] output pins), by pulsing this output pin "high" (for one period of sts3rxd_clk_1) while the sts3txd_pl_1 output pin is pulled "high". if sts-3/stm-1 telecom bus (channel 1) is disabled - rxds3fp_9 (receive ds3 frame pulse input/output - channel 9): if the sts-3/stm-1 telecom bus (channel 1) is disabled and if the ds3/e3 framer block is enabled then this pin will function as the receiving framing referenc e output pin. in this mode, the frame synchronizer block (associated with channel 9) will pulse this output pin "high" for one ds3/e3 bit-period, coinci - dent with the first bit (within a given ds3 or e3 frame) being output via the ds3/e3/sts1_data_out_9 output pin. n ote : this pin is inactive if the frame synchronizer block, associated with channel 9 is by-passed. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 232 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ac20 sts3rxd_c1j1_2 rxds3fp_10 txsts1fp_10 rxsbframe_2 o cmos sts-3/stm-1 receive telecom bus - c1/j1 byte phase indicator output signal - channel 2; ds3/e3 frame syn - chronizer framing pulse output pin - channel 10: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface for channel 2 has been enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 receive telecom bus - c1/j1 byte phase indicator output signal: this output pin pulses "high" under the following two condi - tions. 1. whenever the c1 byte is being output via the sts3rxd_d_2[7:0] output, and 2. whenever the j1 byte is being output via the sts3rxd_d_2[7:0] output. n otes : 1. the sts-3/stm-1 receiv e (drop) telecom bus (associated with channel 2) will indicate that it is transmitting the c1 byte (via the sts3rxd_d_2[7:0] output pins), by pulsing this output pin "high" (for one period of sts3rxd_clk_2) and keeping the sts3rxd_pl_2 output pin pulled "low". 2. the sts-3/stm-1 receiv e (drop) telecom bus (associated with channel 2) will indicate that it is transmitting the j1 byte (via the sts3rxd_d_2[7:0] output pins), by pulsing this output pin "high" (for one period of sts3rxd_clk_2) while the sts3txd_pl_2 output pin is pulled "high". if sts-3/stm-1 telecom bus (channel 2) is disabled - rxds3fp_10 (receive ds3 frame pulse input/output - channel 10): if the sts-3/stm-1 telecom bus (channel 2) is disabled and if the ds3/e3 framer block is enabled then this pin will function as the receiving framing referenc e output pin. in this mode, the frame synchronizer block (associated with channel 10) will pulse this output pin "high" for one ds3/e3 bit-period, coin - cident with the first bit (within a given ds3 or e3 frame) being output via the ds3/e3/sts1_data_out_10 output pin. n ote : this pin is inactive if the frame synchronizer block, associated with channel 10 is by-passed. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 233 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ae14 sts3rxd_c1j1_3 rxds3fp_11 txsts1fp_11 rxsbframe_3 o cmos sts-3/stm-1 receive telecom bus - c1/j1 byte phase indicator output signal - channel 3; ds3/e3 frame syn - chronizer framing pulse output pin - channel 11: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface for channel 3 has been enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 receive telecom bus - c1/j1 byte phase indicator output signal: this output pin pulses "high" under the following two condi - tions. 1. whenever the c1 byte is being output via the sts3rxd_d_3[7:0] output, and 2. whenever the j1 byte is being output via the sts3rxd_d_3[7:0] output. n otes : 1. the sts-3/stm-1 receiv e (drop) telecom bus (associated with channel 3) will indicate that it is transmitting the c1 byte (via the sts3rxd_d_3[7:0] output pins), by pulsing this output pin "high" (for one period of sts3rxd_clk_3) and keeping the sts3rxd_pl_3 output pin pulled "low". 2. the sts-3/stm-1 receiv e (drop) telecom bus (associated with channel 3) will indicate that it is transmitting the j1 byte (via the sts3rxd_d_3[7:0] output pins), by pulsing this output pin "high" (for one period of sts3rxd_clk_3) while the sts3txd_pl_3 output pin is pulled "high". if sts-3/stm-1 telecom bus (channel 3) is disabled - rxds3fp_11 (receive ds3 frame pulse input/output - channel 11): if the sts-3/stm-1 telecom bus (channel 3) is disabled and if the ds3/e3 framer block is enabled then this pin will function as the receiving framing referenc e output pin. in this mode, the frame synchronizer block (associated with channel 11) will pulse this output pin "high" for one ds3/e3 bit-period, coin - cident with the first bit (within a given ds3 or e3 frame) being output via the ds3/e3/sts1_data_out_11 output pin. n ote : this pin is inactive if the frame synchronizer block, associated with channel 11 is by-passed. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 234 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper c22 sts3rxd_dp_0 rxds3fp_4 txsts1fp_4 o cmos sts-3/stm-1 receive (drop) telecom bus - parity output pin - channel 0; ds3/e3 frame synchronizer framing pulse output pin - channel 4: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface for channel 0 has been enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 receive telecom bus - parity output pin: this output pin can be configured to function as one of the fol - lowing. 1. the even or odd parity value of the bits which are output via the sts3rxd_d_0[ 7:0] output pins. 2. the even or odd parity value of the bits which are being output via the sts3rxd_d_0[7:0] output pins and the states of the sts3rxd_pl_0 and sts3rxd_c1j1_0 output pins. this output pin will ultimately be us ed (by drop-side circuitry) to verify the verify of the data wh ich is output via the sts-3/stm- 1 telecom bus interface associated with channel 0. n ote : any one of these configurati on selections can be made by writing the appropriate value into the telecom bus control register (indirect address = 0x00, 0x3b), (direct address = 0x013b). if sts-3/stm-1 telecom bus (channel 0) is disabled - rxds3fp_4 (receive ds3 frame pulse input/output - channel 4): if the sts-3/stm-1 telecom bus (channel 0) is disabled and if the ds3/e3 framer block is enabled then this pin will function as the receiving framing referenc e output pin. in this mode, the frame synchronizer block (associated with channel 4) will pulse this output pin "high" for one ds3/e3 bit-period, coinci - dent with the first bit (within a given ds3 or e3 frame) being output via the ds3/e3/sts1_data_out_4 output pin. n ote : this pin is inactive if the frame synchronizer block, associated with channel 4 is by-passed. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 235 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 g25 sts3rxd_dp_1 rxds3fp_5 txsts1fp_5 o cmos sts-3/stm-1 receive (drop) te lecom bus - parity output pin - channel 1; ds3/e3 fr ame synchronizer framing pulse output pin - channel 5: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface for channel 1 has been enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 receive telecom bus - parity output pin: this output pin can be configured to function as one of the fol - lowing. 1. the even or odd parity value of the bits which are output via the sts3rxd_d_1[7:0] output pins. 2. the even or odd parity value of the bits which are being output via the sts3rxd_d_1[7:0] output pins and the states of the sts3rxd_pl_1 and sts3rxd_c1j1_1 output pins. this output pin will ultimately be us ed (by drop-side circuitry) to verify the verify of the data wh ich is output via the sts-3/stm- 1 telecom bus interface associated with channel 1. n ote : any one of these configurati on selections can be made by writing the appropriate value into the telecom bus control register (indirect address = 0x00, 0x3a), (direct address = 0x013a). if sts-3/stm-1 telecom bus (channel 1) is disabled - rxds3fp_5 (receive ds3 frame pulse input/output - channel 5): if the sts-3/stm-1 telecom bus (channel 1) is disabled and if the ds3/e3 framer block is enabled then this pin will function as the receiving framing referenc e output pin. in this mode, the frame synchronizer block (associated with channel 5) will pulse this output pin "high" for one ds3/e3 bit-period, coinci - dent with the first bit (within a given ds3 or e3 frame) being output via the ds3/e3/sts1_data_out_5 output pin. n ote : this pin is inactive if the frame synchronizer block, associated with channel 5 is by-passed. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 236 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ac23 sts3rxd_dp_2 rxds3fp_6 txsts1fp_6 o cmos sts-3/stm-1 receive (drop) telecom bus - parity output pin - channel 2; ds3/e3 frame synchronizer framing pulse output pin - channel 6: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface for channel 2 has been enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 receive telecom bus - parity output pin: this output pin can be configured to function as one of the fol - lowing. 1. the even or odd parity value of the bits which are output via the sts3rxd_d_2[7:0] output pins .2. the even or odd parity valu e of the bits which are being output via the sts3rxd_d_2[7:0] output pins and the states of the sts3rxd_pl_2 and sts3rxd_c1j1_2 output pins. this output pin will ultimately be us ed (by drop-side circuitry) to verify the verify of the data wh ich is output via the sts-3/stm- 1 telecom bus interface associated with channel 2. n ote : any one of these configurati on selections can be made by writing the appropriate value into the telecom bus control register (indirect address = 0x00, 0x39), (direct address = 0x0139). if sts-3/stm-1 telecom bus (channel 2) is disabled - rxds3fp_6 (receive ds3 frame pulse input/output - channel 6): if the sts-3/stm-1 telecom bus (channel 2) is disabled and if the ds3/e3 framer block is enabled then this pin will function as the receiving framing referenc e output pin. in this mode, the frame synchronizer block (associated with channel 6) will pulse this output pin "high" for one ds3/e3 bit-period, coinci - dent with the first bit (within a given ds3 or e3 frame) being output via the ds3/e3/sts1_data_out_6 output pin. n ote : this pin is inactive if the frame synchronizer block, associated with channel 6 is by-passed. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 237 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ac17 sts3rxd_dp_3 rxds3fp_7 txsts1fp_7 o cmos sts-3/stm-1 receive (drop) te lecom bus - parity output pin - channel 3; ds3/e3 fr ame synchronizer framing pulse output pin - channel 7: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface for channel 3 has been enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 receive telecom bus - parity output pin: this output pin can be configured to function as one of the fol - lowing. 1. the even or odd parity value of the bits which are output via the sts3rxd_d_3[7:0] output pins. 2. the even or odd parity value of the bits which are being output via the sts3rxd_d_3[7:0] output pins and the states of the sts3rxd_pl_3 and sts3rxd_c1j1_3 output pins. this output pin will ultimately be us ed (by drop-side circuitry) to verify the verify of the data wh ich is output via the sts-3/stm- 1 telecom bus interface associated with channel 3. n ote : any one of these configurati on selections can be made by writing the appropriate value into the telecom bus control register (indirect address = 0x00, 0x38), (direct address = 0x0138). if sts-3/stm-1 telecom bus (channel 3) is disabled - rxds3fp_7 (receive ds3 frame pulse input/output - channel 7): if the sts-3/stm-1 telecom bus (channel 3) is disabled and if the ds3/e3 framer block is enabled then this pin will function as the receiving framing referenc e output pin. in this mode, the frame synchronizer block (associated with channel 7) will pulse this output pin "high" for one ds3/e3 bit-period, coinci - dent with the first bit (within a given ds3 or e3 frame) being output via the ds3/e3/sts1_data_out_7 output pin. n ote : this pin is inactive if the frame synchronizer block, associated with channel 7 is by-passed. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 238 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper c20 sts3rxd_alarm_0 rxds3fp_0 txsts1fp_0 o cmos sts-3/stm-1 receive (drop) telecom bus - alarm indica - tor output signal - channel 0; ds3/e3 frame synchronizer framing pulse output pin - channel 0: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface for channel 0 has been enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 receive telecom bus - alarm indicator out - put signal: this output pin pulses "high", coincident with any sts-1 signal (that is being output via the sts3rxd_d_0[7:0] output pins) that is carrying an ais-p indicator. this output pin is "low" for all other conditions. if sts-3/stm-1 telecom bus (channel 0) is disabled - rxds3fp_0 (receive ds3 frame pulse input/output - channel 0): if the sts-3/stm-1 telecom bus (channel 0) is disabled and if the ds3/e3 framer block is enabled then this pin will function as the receiving framing referenc e output pin. in this mode, the frame synchronizer block (associated with channel 0) will pulse this output pin "high" for one ds3/e3 bit-period, coinci - dent with the first bit (within a given ds3 or e3 frame) being output via the ds3/e3/sts1_data_out_0 output pin. n ote : this pin is inactive if the frame synchronizer block, associated with channel 0 is by-passed. e25 sts3rxd_alarm_1 rxds3fp_1 txsts1fp_1 o cmos sts-3/stm-1 receive (drop) telecom bus - alarm indica - tor output signal - channel 1; ds3/e3 frame synchronizer framing pulse output pin - channel 1: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface for channel 1 has been enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 receive telecom bus - alarm indicator out - put signal: this output pin pulses "high", coincident with any sts-1 signal (that is being output via the sts3rxd_d_1[7:0] output pins) that is carrying an ais-p indicator. this output pin is "low" for all other conditions. if sts-3/stm-1 telecom bus (channel 1) is disabled - rxds3fp_1 (receive ds3 frame pulse input/output - channel 1): if the sts-3/stm-1 telecom bus (channel 1) is disabled and if the ds3/e3 framer block is enabled then this pin will function as the receiving framing referenc e output pin. in this mode, the frame synchronizer block (associated with channel 1) will pulse this output pin "high" for one ds3/e3 bit-period, coinci - dent with the first bit (within a given ds3 or e3 frame) being output via the ds3/e3/sts1_data_out_1 output pin. n ote : this pin is inactive if the frame synchronizer block, associated with channel 1 is by-passed. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 239 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 v21 sts3rxd_alarm_2 rxds3fp_2 txsts1fp_2 o cmos sts-3/stm-1 receive (drop) telecom bus - alarm indica - tor output signal - channel 2; ds3/e3 frame synchronizer framing pulse output pin - channel 2: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface for channel 2 has been enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 receive telecom bus - alarm indicator out - put signal: this output pin pulses "high", coincident with any sts-1 signal (that is being output via the sts3rxd_d_2[7:0] output pins) that is carrying an ais-p indicator. this output pin is "low" for all other conditions. if sts-3/stm-1 telecom bus (channel 2) is disabled - rxds3fp_2 (receive ds3 frame pulse input/output - channel 2): if the sts-3/stm-1 telecom bus (channel 2) is disabled and if the ds3/e3 framer block is enabled then this pin will function as the receiving framing referenc e output pin. in this mode, the frame synchronizer block (associated with channel 2) will pulse this output pin "high" for one ds3/e3 bit-period, coinci - dent with the first bit (within a given ds3 or e3 frame) being output via the ds3/e3/sts1_data_out_2 output pin. n ote : this pin is inactive if the frame synchronizer block, associated with channel 2 is by-passed. ad21 sts3rxd_alarm_3 rxds3fp_3 txsts1fp_3 o cmos sts-3/stm-1 receive (drop) telecom bus - alarm indica - tor output signal - channel 3; ds3/e3 frame synchronizer framing pulse output pin - channel 3: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface for channel 3 has been enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 receive telecom bus - alarm indicator out - put signal: this output pin pulses "high", coincident with any sts-1 signal (that is being output via the sts3rxd_d_3[7:0] output pins) that is carrying an ais-p indicator. this output pin is "low" for all other conditions. if sts-3/stm-1 telecom bus (channel 3) is disabled - rxds3fp_3 (receive ds3 frame pulse input/output - channel 3): if the sts-3/stm-1 telecom bus (channel 3) is disabled and if the ds3/e3 framer block is enabled then this pin will function as the receiving framing referenc e output pin. in this mode, the frame synchronizer block (associated with channel 3) will pulse this output pin "high" for one ds3/e3 bit-period, coinci - dent with the first bit (within a given ds3 or e3 frame) being output via the ds3/e3/sts1_data_out_3 output pin. n ote : this pin is inactive if the frame synchronizer block, associated with channel 3 is by-passed. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 240 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper b21 sts3rxd_d_0_0 txlev_0 rxsbdata_0 o cmos receive sts-3/stm-1 telecom bus - channel 0 - output data bus pin number 0/txlev_0 (general purpose) out - put pin: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 0: stsrxd_d_0_0: this output pin along with sts3 rxd_d_0[7:1] function as the sts-3/stm-1 receive (drop) te lecom bus - output data bus for channel 0. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_0. n ote : this input pin functions as the lsb (least significant bit) of the receive (drop) telecom bus for channel 0. if sts-3/stm-1 telecom bus (channel 0) is disabled - txlev_0 (general purpose) output pin. this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 2 (txlev) within the line interface drive register associated with channel 0 (indirect address = 0x1e, 0x80), (direct address = 0x1f80). n ote : for product legacy purposes, this pin is called txlev_0 because one possible application is to tie this output pin to a txlev (transmit line build-out disable) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 241 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 b20 sts3rxd_d_0_1 encodis_0 rxsbdata_1 o cmos receive sts-3/stm-1 telecom bus - channel 0 - output data bus pin number 1/encodis_0 (general purpose) output pin: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 1: stsrxd_d_0_1: this output pin along with sts3rxd_d_0[7:2] and sts3rxd_d_0_0 function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 0. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - encodis_0 (general purpose) output pin. this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 3 (encodis) within the line inter - face drive register associated with channel 0 (indirect address = 0x1e, 0x80), (direct address = 0x1f80). n ote : for product legacy purposes, this pin is called encodis_0 because one possible application is to tie this output pin to an encodis (b3zs/hdb3 encoder disable) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 242 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper e20 sts3rxd_d_0_2 ds3/e3/ sts1_data_out_0 rxsbdata_2 o cmos receive sts-3/stm-1 telecom bus - channel 0 - output data bus pin number 2/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 0 (ds3/e3/sts1_data_out_0): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 2: stsrxd_d_0_2: this output pin along with sts3rxd_d_0[7:3] and sts3rxd_d_0[1:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 0. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/ e3/sts1_data_out line interface data output pin - channel 0: this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/ sts-1 liu ic. this output pin should be connected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspond - ing to channel 0). by default, the data that is output via this output pin will be updated upon the rising edge of ds3/e3/ sts1_clk_out_0 signal pin number c21. for ds3/e3 applications the xrt94l43 can be configured to update this output signal upon the falling edge of the ds3/e3/sts1_clk_0 signal by setting bit 2 (ds3/e3/sts1_clk _out invert), within the i/o control register - channel 0 (indirect address = 0x1e, 0x01), (direct address = 0x1f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_0 signal upon the falling edge of ds3/e3/ sts1_clk_out_0. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 243 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 d20 sts3rxd_d_0_3 ds3/e3/ sts1_data_out_4 rxsbdata_3 o cmos receive sts-3/stm-1 telecom bus - channel 0 - output data bus pin number 3/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 4 (ds3/e3/sts1_data_out_4): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 3: stsrxd_d_0_3: this output pin along with sts3rxd_d_0[7:4] and sts3rxd_d_0[2:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 0. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/ e3/sts1_data_out line interface data output pin - channel 4: this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/ sts-1 liu ic. this output pin should be connected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspond - ing to channel 4). by default, the data that is output via this output pin will be updated upon th e rising edge of the ds3/e3/ sts1_clk_out_4 signal pin number e21. for ds3/e3 applications the xrt94l43 can be configured to update this output signal upon the falling edge of the ds3/e3/sts1_clk_4 signal by setting bit 2 (ds3/e3/sts1_clk _out invert), within the i/o control register - channel 4 (indirect address = 0x5e, 0x01), (direct address = 0x5f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_4 signal upon the falling edge of ds3/e3/ sts1_clk_out_4. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 244 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper d21 sts3rxd_d_0_4 ds3/e3/ sts1_data_out_8 rxsbdata_4 o cmos receive sts-3/stm-1 telecom bus - channel 0 - output data bus pin number 4/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 8 (ds3/e3/sts1_data_out_8): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 4: stsrxd_d_0_4: this output pin along with sts3rxd_d_0[7:5] and sts3rxd_d_0[3:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 0. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/ e3/sts1_data_out line interface data output pin - channel 8: this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/ sts-1 liu ic. this output pin should be connected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspond - ing to channel 8). by default, th e data that is being output via this output pin will be updated upon the rising edge of the ds3/ e3/sts-1_clk_out_8 signal pin number c24. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/ sts1_data_8 output signal upon the falling edge of the ds3/ e3/sts1_clk_8 signal by setting bit 2 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 8 (indirect address = 0x9e, 0x01), (direct address = 0x9f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_8 signal upon the falling edge of ds3/e3/ sts1_clk_out_8. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 245 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 c21 sts3rxd_d_0_5 ds3/e3/sts1_clk_out_0 rxsbdata_5 o cmos receive sts-3/stm-1 telecom bus - channel 0 - output data bus pin number 5/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 0: (ds3/e3/sts1_clk_out_0): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 5: stsrxd_d_0_5: this output pin along with sts3rxd_d_0[7:6] and sts3rxd_d_0[4:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 0. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/ e3/sts1_clk_out line interface clock output pin - channel 0: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/ e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 0). by default, the data, which is being output via the ds3/e3/ sts1_data_out_0 output pin will be updated upon the rising edge of this clock output signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/ sts1_data_0 output signal upon the falling edge of the ds3/ e3/sts1_clk_0 signal by setting bit 0 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 0 (indirect address = 0x1e, 0x01), (direct address = 0x1f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_0 signal upon the falling edge of ds3/e3/ sts1_clk_0. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 246 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper e21 sts3rxd_d_0_6 ds3/e3/sts1_clk_out_4 rxsbdata_6 o cmos receive sts-3/stm-1 telecom bus - channel 0 - output data bus pin number 6/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 4: (ds3/e3/sts1_clk_out_4): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 6: stsrxd_d_0_6: this output pin along with sts3rxd_d_0_7 and sts3rxd_d_0[5:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 0. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_0. if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/ e3/sts1_clk_out line interface clock output pin - channel 4: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/ e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 4). by default, the data, which is being output via the ds3/e3/ sts1_data_out_4 output pin will be updated upon the rising edge of this clock output signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/ sts1_data_4 output signal upon the falling edge of the ds3/ e3/sts1_clk_4 signal by setting bit 0 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 4 (indirect address = 0x5e, 0x01), (direct address = 0x5f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_4 signal upon the falling edge of ds3/e3/ sts1_clk_4. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 247 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 c24 sts3rxd_d_0_7 ds3/e3/sts1_clk_out_8 rxsbdata_7 o cmos receive sts-3/stm-1 telecom bus - channel 0 - output data bus pin number 7/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 8: (ds3/e3/sts1_clk_out_8): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 0 is enabled. if sts-3/stm-1 telecom bus (channel 0) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 7: stsrxd_d_0_7: this output pin along with sts3 rxd_d_0[6:0] function as the sts-3/stm-1 receive (drop) te lecom bus - output data bus for channel 0. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_0. n ote : this output pin functions as the msb (most significant bit) for the sts-3/stm-1 re ceive (drop) telecom bus interface - output data bus (channel 0). if sts-3/stm-1 telecom bus (channel 0) is disabled - ds3/ e3/sts1_clk_out line interface clock output pin - channel 8: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/ e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 8). by default, the data, which is being output via the ds3/e3/ sts1_data_out_8 output pin will be updated upon the rising edge of this clock output signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/ sts1_data_8 output signal upon the falling edge of the ds3/ e3/sts1_clk_8 signal by setting bit 0 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 8 (indirect address = 0x9e, 0x01), (direct address = 0x9f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_8 signal upon the falling edge of ds3/e3/ sts1_clk_8. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 248 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper e24 sts3rxd_d_1_0 txlev_1 rxsbdata_0 o cmos receive sts-3/stm-1 telecom bus - channel 1 - output data bus pin number 0/txlev_1 (general purpose) out - put pin: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 0: stsrxd_d_1_0: this output pin along with sts3 rxd_d_1[7:1] function as the sts-3/stm-1 receive (drop) te lecom bus - output data bus for channel 1. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_1. n ote : this input pin functions as the lsb (least significant bit) of the receive (drop) telecom bus for channel 1. if sts-3/stm-1 telecom bus (channel 1) is disabled - txlev_1 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 2 (txlev) within the line interface drive register associated with channel 1 (indirect address = 0x2e, 0x80), (direct address = 0x2f80). n ote : for product legacy purposes, this pin is called txlev_1 because one possible application is to tie this output pin to a txlev (transmit line build-out disable) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 249 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 e23 sts3rxd_d_1_1 encodis_1 rxsbdata_1 o cmos receive sts-3/stm-1 telecom bus - channel 1 - output data bus pin number 1/encodis_1 (general purpose) output pin: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 1: stsrxd_d_1_1: this output pin along with sts3rxd_d_1[7:2] and sts3rxd_d_1_0 function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 1. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - encodis_1 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 3 (encodis) within the line inter - face drive register associated with channel 1 (indirect address = 0x2e, 0x80), (direct address = 0x2f80). n ote : for product legacy purposes, this pin is called encodis_1 because one possible application is to tie this output pin to an encodis (b3zs/hdb3 encoder disable) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 250 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper f26 sts3rxd_d_1_2 ds3/e3/ sts1_data_out_1 rxsbdata_2 o cmos receive sts-3/stm-1 telecom bus - channel 1 - output data bus pin number 2/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 1 (ds3/e3/sts1_data_out_1): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 2: stsrxd_d_1_2: this output pin along with sts3rxd_d_1[7:3] and sts3rxd_d_1[1:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 1. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/ e3/sts1_data_out line interface data output pin - channel 1: this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/ sts-1 liu ic. this output pin should be connected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspond - ing to channel 1). by default, the data that is output via this output pin will be updated upon the rising edge of the ds3/e3/ sts1_clk_out_1 signal pin number g26. for ds3/e3 applications the xrt94l43 can be configured to update this output signal upon the falling edge of the ds3/e3/sts1_clk_1 signal by setting bit 2 (ds3/e3/sts1_clk _out invert), within the i/o control register - channel 1 (indirect address = 0x2e, 0x01), (direct address = 0x2f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_1 signal upon the falling edge of ds3/e3/ sts1_clk_out_1. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 251 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 h26 sts3rxd_d_1_3 ds3/e3/ sts1_data_out_5 rxsbdata_3 o cmos receive sts-3/stm-1 telecom bus - channel 1 - output data bus pin number 3/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 5 (ds3/e3/sts1_data_out_5): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 3: stsrxd_d_1_3: this output pin along with sts3rxd_d_1[7:4] and sts3rxd_d_1[2:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 1. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/ e3/sts1_data_out line interface data output pin - channel 5. this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/ sts-1 liu ic. this output pin should be connected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspond - ing to channel 5). by default, the data that is output via this output pin will be updated upon th e rising edge of the ds3/e3/ sts1_clk_out_5 signal pin number f25. for ds3/e3 applications the xrt94l43 can be configured to update this output signal upon the falling edge of the ds3/e3/sts1_clk_5 signal by setting bit 2 (ds3/e3/sts1_clk _out invert), within the i/o control register - channel 5 (indirect address = 0x6e, 0x01), (direct address = 0x6f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_5 signal upon the falling edge of ds3/e3/ sts1_clk_out_5. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 252 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper j26 sts3rxd_d_1_4 ds3/e3/ sts1_data_out_9 rxsbdata_4 o cmos receive sts-3/stm-1 telecom bus - channel 1 - output data bus pin number 4/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 9 (ds3/e3/sts1_data_out_9): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 4: stsrxd_d_1_4: this output pin along with sts3rxd_d_1[7:5] and sts3rxd_d_1[3:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 1. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/ e3/sts1_data_out line interface data output pin - channel 9. this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/ sts-1 liu ic. this output pin should be connected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspond - ing to channel 9). by default, th e data that is being output via this output pin will be updated upon the rising edge of the ds3/ e3/sts-1_clk_out_9 signal pin number h25. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/ sts1_data_9 output signal upon the falling edge of the ds3/ e3/sts1_clk_9 signal by setting bit 2 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 9 (indirect address = 0xae, 0x01), (direct address = 0xaf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_9 signal upon the falling edge of ds3/e3/ sts1_clk_out_9. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 253 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 g26 sts3rxd_d_1_5 ds3/e3/sts1_clk_out_1 rxsbdata_5 o cmos receive sts-3/stm-1 telecom bus - channel 1 - output data bus pin number 5/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 1: (ds3/e3/sts1_clk_out_1): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 5: stsrxd_d_1_5: this output pin along with sts3rxd_d_1[7:6] and sts3rxd_d_1[4:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 1. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/ e3/sts1_clk_out line interface clock output pin - channel 1: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/ e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 1). by default, the data, which is being output via the ds3/e3/ sts1_data_out_1 output pin will be updated upon the rising edge of this clock output signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/ sts1_data_1 output signal upon the falling edge of the ds3/ e3/sts1_clk_1 signal by setting bit 0 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 1 (indirect address = 0x2e, 0x01), (direct address = 0x2f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_1 signal upon the falling edge of ds3/e3/ sts1_clk_1. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 254 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper f25 sts3rxd_d_1_6 ds3/e3/sts1_clk_out_5 rxsbdata_6 o cmos receive sts-3/stm-1 telecom bus - channel 1 - output data bus pin number 6/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 5: (ds3/e3/sts1_clk_out_5): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 6: stsrxd_d_1_6: this output pin along with sts3rxd_d_1_7 and sts3rxd_d_1[5:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 1. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_1. if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/ e3/sts1_clk_out line interface clock output pin - channel 5: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/ e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 5). by default, the data, which is being output via the ds3/e3/ sts1_data_out_5 output pin will be updated upon the rising edge of this clock output signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/ sts1_data_5 output signal upon the falling edge of the ds3/ e3/sts1_clk_5 signal by setting bit 0 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 5 (indirect address = 0x6e, 0x01), (direct address = 0x6f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_5 signal upon the falling edge of ds3/e3/ sts1_clk_5. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 255 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 h25 sts3rxd_d_1_7 ds3/e3/sts1_clk_out_9 rxsbdata_7 o cmos receive sts-3/stm-1 telecom bus - channel 1 - output data bus pin number 7/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 9: (ds3/e3/sts1_clk_out_9): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 1 is enabled. if sts-3/stm-1 telecom bus (channel 1) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 7: stsrxd_d_1_7: this output pin along with sts3 rxd_d_1[6:0] function as the sts-3/stm-1 receive (drop) te lecom bus - output data bus for channel 1. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_1. n ote : this output pin functions as the msb (most significant bit) for the sts-3/stm-1 re ceive (drop) telecom bus interface - output data bus (channel 1). if sts-3/stm-1 telecom bus (channel 1) is disabled - ds3/ e3/sts1_clk_out line interface clock output pin - channel 9: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/ e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 9). by default, the data, which is being output via the ds3/e3/ sts1_data_out_9 output pin will be updated upon the rising edge of this clock output pin. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/ sts1_data_9 output signal upon the falling edge of the ds3/ e3/sts1_clk_9 signal by setting bit 0 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 9 (indirect address = 0xae, 0x01), (direct address = 0xaf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_9 signal upon the falling edge of ds3/e3/ sts1_clk_9. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 256 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper y24 sts3rxd_d_2_0 txlev_2 rxsbdata_0 o cmos receive sts-3/stm-1 telecom bus - channel 2 - output data bus pin number 0/txlev_2 (general purpose) out - put pin: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 0: stsrxd_d_2_0: this output pin along with sts3 rxd_d_2[7:1] function as the sts-3/stm-1 receive (drop) te lecom bus - output data bus for channel 2. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_2. n ote : this input pin functions as the lsb (least significant bit) of the receive (drop) telecom bus for channel 2. if sts-3/stm-1 telecom bus (channel 2) is disabled - txlev_2 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 2 (txlev) within the line interface drive register associated with channel 2 (indirect address = 0x3e, 0x80), (direct address = 0x3f80). n ote : for product legacy purposes, this pin is called txlev_2 because one possible application is to tie this output pin to a txlev (transmit line build-out disable) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 257 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 y23 sts3rxd_d_2_1 encodis_2 rxsbdata_1 o cmos receive sts-3/stm-1 telecom bus - channel 2 - output data bus pin number 1/encodis_2 (general purpose) output pin: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 1: stsrxd_d_2_1: this output pin along with sts3rxd_d_2[7:2] and sts3rxd_d_2_0 function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 2. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - encodis_2 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 3 (encodis) within the line inter - face drive register associated with channel 2 (indirect address = 0x3e, 0x80), (direct address = 0x3f80). n ote : for product legacy purposes, this pin is called encodis_2 because one possible application is to tie this output pin to an encodis (b3zs/hdb3 encoder disable) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 258 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper w24 sts3rxd_d_2_2 ds3/e3/ sts1_data_out_2 rxsbdata_2 o cmos receive sts-3/stm-1 telecom bus - channel 2 - output data bus pin number 2/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 1 (ds3/e3/sts1_data_out_2): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 2: stsrxd_d_2_2: this output pin along with sts3rxd_d_2[7:3] and sts3rxd_d_2[1:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 2. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/ e3/sts1_data_out line interface data output pin - channel 2. this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/ sts-1 liu ic. this output pin should be connected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspond - ing to channel 2). by default, the data that is output via this output pin will be updated upon the rising edge of the ds3/e3/ sts1_clk_out_2 signal pin number ac25. for ds3/e3 applications for ds3/e3 applications the xrt94l43 can be configured to update this output signal upon the falling edge of the ds3/e3/ sts1_clk_2 signal by setting bit 2 (ds3/e3/sts1_clk_out invert), within the i/o control register - channel 2 (indirect address = 0x3e, 0x01), (direct address = 0x3f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_2 signal upon the falling edge of ds3/e3/ sts1_clk_out_2. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 259 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ac24 sts3rxd_d_2_3 ds3/e3/ sts1_data_out_6 rxsbdata_3 o cmos receive sts-3/stm-1 telecom bus - channel 2 - output data bus pin number 3/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 6 (ds3/e3/sts1_data_out_6): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 3: stsrxd_d_2_3: this output pin along with sts3rxd_d_2[7:4] and sts3rxd_d_2[2:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 2. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/ e3/sts1_data_out line interface data output pin - channel 6. this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/ sts-1 liu ic. this output pin should be connected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspond - ing to channel 6). by default, the data that is output via this pin will be updated upon the risi ng edge of the ds3/e3/ sts1_clk_out_6 signal pin number aa22. for ds3/e3 applications the xrt94l43 can be configured to update this output signal upon the falling edge of the ds3/e3/sts1_clk_6 signal by setting bit 2 (ds3/e3/sts1_clk _out invert), within the i/o control register - channel 6 (indirect address = 0x7e, 0x01), (direct address = 0x7f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_6 signal upon the falling edge of ds3/e3/ sts1_clk_out_6. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 260 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ac21 sts3rxd_d_2_4 ds3/e3/ sts1_clk_out_10 rxsbdata_4 o cmos receive sts-3/stm-1 telecom bus - channel 2 - output data bus pin number 4/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 10 (ds3/e3/sts1_data_out_10): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 4: stsrxd_d_2_4: this output pin along with sts3rxd_d_2[7:5] and sts3rxd_d_2[3:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 2. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/ e3/sts1_data_out line interface data output pin - channel 10. this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/ sts-1 liu ic. this output pin should be connected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspond - ing to channel 10). by default, the data that is being output via the ds3/e3/sts1_data_out_10 output pin will be updated upon the rising edge of this output clock signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/ sts1_data_10 output signal upon the falling edge of the ds3/ e3/sts1_clk_10 signal by setting bit 2 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 10 (indirect address = 0xbe, 0x01), (direct address = 0xbf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_10 signal upon the falling edge of ds3/e3/ sts1_clk_out_10. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 261 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ac25 sts3rxd_d_2_5 ds3/e3/sts1_clk_out_2 rxsbdata_5 o cmos receive sts-3/stm-1 telecom bus - channel 2 - output data bus pin number 5/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 2: (ds3/e3/sts1_clk_out_2): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 5: stsrxd_d_2_5: this output pin along with sts3rxd_d_2[7:6] and sts3rxd_d_2[4:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 2. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/ e3/sts1_clk_out line interface clock output pin - channel 2: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/ e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 2). by default, the data, which is being output via the ds3/e3/ sts1_data_out_2 output pin will be updated upon the rising edge of this output clock signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/ sts1_data_2 output signal upon the falling edge of the ds3/ e3/sts1_clk_2 signal by setting bit 0 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 2 (indirect address = 0x3e, 0x01), (direct address = 0x3f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_2 signal upon the falling edge of ds3/e3/ sts1_clk_2. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 262 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper aa22 sts3rxd_d_2_6 ds3/e3/sts1_clk_out_6 rxsbdata_6 o cmos receive sts-3/stm-1 telecom bus - channel 2 - output data bus pin number 6/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 6: (ds3/e3/sts1_clk_out_6): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 6: stsrxd_d_2_6: this output pin along with sts3rxd_d_2_7 and sts3rxd_d_2[5:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 2. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_2. if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/ e3/sts1_clk_out line interface clock output pin - channel 6: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/ e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 6). by default, the data, which is being output via the ds3/e3/ sts1_data_out_6 output pin will be updated upon the rising edge of this output clock signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/ sts1_data_6 output signal upon the falling edge of the ds3/ e3/sts1_clk_6 signal by setting bit 0 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 6 (indirect address = 0x7e, 0x01), (direct address = 0x7f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_6 signal upon the falling edge of ds3/e3/ sts1_clk_6. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 263 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ae23 sts3rxd_d_2_7 ds3/e3/ sts1_clk_out_10 rxsbdata_7 o cmos receive sts-3/stm-1 telecom bus - channel 2 - output data bus pin number 7/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 10: (ds3/e3/sts1_clk_out_10): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 2 is enabled. if sts-3/stm-1 telecom bus (channel 2) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 7: stsrxd_d_2_7: this output pin along with sts3 rxd_d_2[6:0] function as the sts-3/stm-1 receive (drop) te lecom bus - output data bus for channel 2. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_2. n ote : this output pin functions as the msb (most significant bit) for the sts-3/stm-1 re ceive (drop) telecom bus interface - output data bus (channel 2). if sts-3/stm-1 telecom bus (channel 2) is disabled - ds3/ e3/sts1_clk_out line interface clock output pin - channel 10: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/ e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 10). by default, the data, which is being output via the ds3/e3/ sts1_data_out_10 output pin will be updated upon the ris - ing edge of this output clock signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/ sts1_data_10 output signal upon the falling edge of the ds3/ e3/sts1_clk_10 signal by setting bit 0 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 10 (indirect address = 0xbe, 0x01), (direct address = 0xbf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_10 signal upon the falling edge of ds3/e3/ sts1_clk_10. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 264 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ae21 sts3rxd_d_3_0 txlev_3 rxsbdata_0 o cmos receive sts-3/stm-1 telecom bus - channel 3 - output data bus pin number 0/txlev_3 (general purpose) out - put pin: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 0: stsrxd_d_3_0: this output pin along with sts3 rxd_d_3[7:1] function as the sts-3/stm-1 receive (drop) te lecom bus - output data bus for channel 3. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_3. n ote : this input pin functions as the lsb (least significant bit) of the receive (drop) telecom bus for channel 3. if sts-3/stm-1 telecom bus (channel 3) is disabled - txlev_3 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 2 (txlev) within the line interface drive register associated with channel 3 (indirect address = 0x4e, 0x80), (direct address = 0x4f80). n ote : for product legacy purposes, this pin is called txlev_3 because one possible application is to tie this output pin to a txlev (transmit line build-out disable) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 265 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ac19 sts3rxd_d_3_1 encodis_3 rxsbdata_1 o cmos receive sts-3/stm-1 telecom bus - channel 3 - output data bus pin number 1/encodis_3 (general purpose) output pin: the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 1: stsrxd_d_3_1: this output pin along with sts3rxd_d_3[7:2] and sts3rxd_d_3_0 function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 3. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - encodis_3 (general purpose) output pin: this output pin can be used as a general purpose output pin. the state of this output pin can be controlled by writing the appropriate value into bit 3 (encodis) within the line inter - face drive register associated with channel 3 (indirect address = 0x4e, 0x80), (direct address = 0x4f80). n ote : for product legacy purposes, this pin is called encodis_3 because one possible application is to tie this output pin to an encodis (b3zs/hdb3 encoder disable) input pin from one of exar's xrt73l0x/ xrt75l0x ds3/e3/sts-1 liu devices. however, this output pin, and the corresponding register bit can be used for any purpose. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 266 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ab21 sts3rxd_d_3_2 ds3/e3/ sts1_data_out_3 rxsbdata_2 o cmos receive sts-3/stm-1 telecom bus - channel 3 - output data bus pin number 2/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 3 (ds3/e3/sts1_data_out_3): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 2: stsrxd_d_3_2: this output pin along with sts3rxd_d_3[7:3] and sts3rxd_d_3[1:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 3. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/ e3/sts1_data_out line interface data output pin - channel 3. this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/ sts-1 liu ic. this output pin should be connected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspond - ing to channel 3). by default, the data that is output via this pin will be updated upon the rising edge of the ds3/e3/ sts1_clk_out_3 signal pin number ab20. for ds3/e3 applications the xrt94l43 can be configured to update this output signal upon the falling edge of the ds3/e3/sts1_clk_3 signal by setting bit 2 (ds3/e3/sts1_clk _out invert), within the i/o control register - channel 3 (indirect address = 0x4e, 0x01), (direct address = 0x4f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_3 signal upon the falling edge of ds3/e3/ sts1_clk_out_3. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 267 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ae18 sts3rxd_d_3_3 ds3/e3/ sts1_data_out_7 rxsbdata_3 o cmos receive sts-3/stm-1 telecom bus - channel 3 - output data bus pin number 3/ds3/e3 framer or transmit sts-1 toh processor block line interface output pin - channel 7 (ds3/e3/sts1_data_out_7): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 3: stsrxd_d_3_3: this output pin along with sts3rxd_d_3[7:4] and sts3rxd_d_3[2:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 3. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/ e3/sts1_data_out line interface data output pin - channel 6. this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/ sts-1 liu ic. this output pin should be connected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspond - ing to channel 7). by default, the data that is output via this pin will be updated upon the risi ng edge of the ds3/e3/ sts1_clk_out_7 signal pin number ad19. for ds3/e3 applications the xrt94l43 can be configured to update this output signal upon the falling edge of the ds3/e3/sts1_clk_7 signal by setting bit 2 (ds3/e3/sts1_clk _out invert), within the i/o control register - channel 7 (indirect address = 0x8e, 0x01), (direct address = 0x8f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_7 signal upon the falling edge of ds3/e3/ sts1_clk_out_7. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 268 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ae15 sts3rxd_d_3_4 ds3/e3/ sts1_data_out_11 rxsbdata_4 o cmos receive sts-3/stm-1 telecom bus - channel 3 - output data bus pin number 4/ds3/e3 framer or transmit sts-1 toh processor block line interf ace output pin - channel 11 (ds3/e3/sts1_data_out_11): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 4: stsrxd_d_3_4: this output pin along with sts3rxd_d_3[7:5] and sts3rxd_d_3[3:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 3. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/ e3/sts1_data_out line interface data output pin - channel 1. this pin outputs single-rail ds3, e3 or sts-1 data to a ds3/e3/ sts-1 liu ic. this output pin should be connected to the tpos/tdata input of the ds3/e3/sts-1 liu ic (correspond - ing to channel 11). by default, the data that is being output via this output pin will be updated upon the rising edge of the ds3/ e3/sts-1_clk_out_11 signal pin number ab15. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/ sts1_data_11 output signal upon the falling edge of the ds3/ e3/sts1_clk_11 signal by setting bit 2 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 11 (indirect address = 0xce, 0x01), (direct address = 0xcf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_11 signal upon the falling edge of ds3/e3/ sts1_clk_out_11. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 269 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ab20 sts3rxd_d_3_5 ds3/e3/sts1_clk_out_3 rxsbdata_5 o cmos receive sts-3/stm-1 telecom bus - channel 3 - output data bus pin number 5/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 3: (ds3/e3/sts1_clk_out_3): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 5: stsrxd_d_3_5: this output pin along with sts3rxd_d_3[7:6] and sts3rxd_d_3[4:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 3. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/ e3/sts1_clk_out line interface clock output pin - channel 3: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/ e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 3). by default, the data, which is being output via the ds3/e3/ sts1_data_out_3 output pin will be updated upon the rising edge of this output pin. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/ sts1_data_3 output signal upon the falling edge of the ds3/ e3/sts1_clk_3 signal by setting bit 0 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 3 (indirect address = 0x4e, 0x01), (direct address = 0x4f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_3 signal upon the falling edge of ds3/e3/ sts1_clk_3. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 270 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ad19 sts3rxd_d_3_6 ds3/e3/sts1_clk_out_7 rxsbdata_6 o cmos receive sts-3/stm-1 telecom bus - channel 3 - output data bus pin number 6/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 7: (ds3/e3/sts1_clk_out_7): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 6: stsrxd_d_3_6: this output pin along with sts3rxd_d_3_7 and sts3rxd_d_3[5:0] function as the sts-3/stm-1 receive (drop) telecom bus - output data bus for channel 3. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_3. if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/ e3/sts1_clk_out line interface clock output pin - channel 7: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/ e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 7). by default, the data, which is being output via the ds3/e3/ sts1_data_out_7 output pin will be updated upon the rising edge of this output pin. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/ sts1_data_6 output signal upon the falling edge of the ds3/ e3/sts1_clk_7 signal by setting bit 0 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 7 (indirect address = 0x8e, 0x01), (direct address = 0x8f01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_7 signal upon the falling edge of ds3/e3/ sts1_clk_7. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 271 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ab15 sts3rxd_d_3_7 ds3/e3/sts1_clk_out_11 rxsbdata_7 o cmos receive sts-3/stm-1 telecom bus - channel 3 - output data bus pin number 7/ds3/e3 framer or transmit sts-1 toh processor block line interface clock output pin - channel 11: (ds3/e3/sts1_clk_out_11): the function of this output pi n depends upon whether or not thests-3/stm-1 telecom bus interface, associated with channel 3 is enabled. if sts-3/stm-1 telecom bus (channel 3) has been enabled - sts-3/stm-1 receive telecom bus - output data bus pin number 7: stsrxd_d_3_7: this output pin along with sts3 rxd_d_3[6:0] function as the sts-3/stm-1 receive (drop) te lecom bus - output data bus for channel 3. the sts-3/stm-1 telecom bus interface will update the data via this output upon the rising edge of sts3rxd_clk_3. n ote : this output pin functions as the msb (most significant bit) for the sts-3/stm-1 re ceive (drop) telecom bus interface - output data bus (channel 3). if sts-3/stm-1 telecom bus (channel 3) is disabled - ds3/ e3/sts1_clk_out line interface clock output pin - channel 11: this pin outputs a ds3, e3 or sts-1 rate clock signal to a ds3/ e3/sts-1 liu ic. this output pin should be connected to the txclk input of the ds3/e3/sts-1 liu ic (corresponding to channel 11). by default, the data, which is being output via the ds3/e3/ sts1_data_out_11 output pin will be updated upon the ris - ing edge of this clock output signal. for ds3/e3 applications the xrt94l43 can be configured to update the ds3/e3/ sts1_data_11 output signal upon the falling edge of the ds3/ e3/sts1_clk_11 signal by setting bit 0 (ds3/e3/ sts1_clk_out invert), within the i/o control register - channel 11 (indirect address = 0xce, 0x01), (direct address = 0xcf01) to a "1". for sts-1 applications the xrt94l43 can not be configured to update the ds3/e3/ sts1_data_out_11 signal upon the falling edge of ds3/e3/ sts1_clk_11. sts-3/stm-1 telecom bus interface - receive direction p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 272 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper receive transport overhead interface p in # s ignal n ame i/o s ignal t ype d escription y5 rxtohclk o cmos receive toh output port - clock output: this output pin, along with rxtoh, rxtohvalid and rxtohframe func - tion as the receive toh output port: the receive toh output port is us ed to obtain the value of the toh bytes, within the incoming sts-12/stm-4 signal. this output pin provides a clock signal. if the rxtohvalid output pin is "high" , then the contents of the toh bytes within the incoming sts-12 data-stream, will be serially output via the rxtoh output. this data will be updated upon the falling edge of this clock signal. therefore, it is advisable to sample the data (at the rxtoh output pin) upon the rising edge of this clock output signal. w5 rxtohvalid o cmos receive toh output port - toh valid (or ready) indicator: this output pin, along with rxtoh and rxtohframe function as the receive toh output port. this output pin will toggle "high" whenev er valid toh data is being output via the rxtoh output pin. v6 rxtoh o cmos receive toh output port - output pin: this output pin, along with rxtohclk, rxtohvalid and rxtohframe function as the receive toh output port. all toh data, that resides within the incoming sts-12 data-stream will be output via this output pin. the rxtohvalid output pin will toggle "high", coincident with anytime a bit (from the receive sts-12 toh data) is being output via this output pin. the rxtohframe output pin will pulse "high" (for eight periods of rxto - hclk) coincident to when the a1 byte is being output via this output pin. data, on this output pin, is updated upon the falling edge of rxtohclk. w6 rxtohframe o cmos receive toh output port - sts-12/stm-4 frame indicator: this output pin, along with the rxtohc lk, rxtohvalid and rxtoh output pins function as the receive toh output port. this output pin will pulse "high", for one period of rxtohclk, one rxto - hclk period prior to the very first toh bit (of a given sts-12 frame) being output via the rxtoh output pin. w2 rxldccval o cmos receive - line dcc output port - dcc value indicator output pin: this output pin, along with the rxto hclk and the rxldcc output pins function as the receive line dcc output port of the xrt94l43. this output pin pulses "high" coincident to when the receive line dcc output port outputs a dcc bit via the rxldcc output pin. this output pin is updated u pon the falling edge of rxtohclk. the line dcc hdlc controller circuitry th at is interfaced to this output pin, the rxldcc and the rxtohclk pins is suppose to do the following. 1. it should continuously sample and monitor the state of this output pin upon the rising edge of rxtohclk. 2. anytime the line dcc hdlc circuitry samples this output pin being "high", it should sample and latch the data on the rxldcc output pin (as a valid line dcc bit) into the line dcc hdlc circuitry.
xrt94l43 273 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 w3 rxldcc o cmos receive - line dcc output port - output pin: this output pin, along with rxldccv al and the rxtohclk output pins function as the receive line dcc output port of the xrt94l43. this pin outputs the contents of the line dcc (e.g., the d4, d5, d6, d7, d8, d9, d10, d11 and d12 bytes), within the incoming sts-12 data- stream. the receive line dcc output port will assert the rxldccval output pin, in order to indicate that the data, residing on the rxldcc out - put pin is a valid line dcc byte. the receive line dcc output port will update the rxldccval and the rxldcc output pins upon the falling edge of the rxtohclk output pin. t he line dcc hdlc circuitry that is interfaced to this output pin, the rxldccval and the rxtohclk pins is suppose to do the following. 1. it should continuously sample and monitor the state of the rxldccval output pin upon the rising edge of rxtohclk. 2. anytime the line dcc hdlc circuitry samples the rxldccval output pin "high", it should sample and latch the contents of this output pin (as a valid line dcc bit) into the line dcc hdlc circuitry. y1 rxe1f1e2fp o cmos receive - order-wire output port - frame boundary indicator: this output pin, along with rxe1f1e2, rxe1f1e2val and the rxtohclk output pins function as the rece ive order-wire output port of the xrt94l43. this output pin pulses "high" (for one period of rxtohclk) coincident to when the very first bit (of the e1 byte) is being output via the rxe1f1e2 output pin. y2 rxe1f1e2 o cmos receive - order-wire output port - output pin: this output pin, along with rxe1f1e2val, rxe1f1f2fp, and the rxto - hclk output pins function as the re ceive order-wire output port of the xrt94l43. this pin outputs the contents of the order-wire bytes (e.g., the e1, f1 and e2 bytes) within the incoming sts-12 data-stream. the receive order-wire output port will pulse the rxe1f1e2fp output pin "high" (for one period of rxtohclk) coincident to when the very first bit (of the e1 byte) is being output via the rxe1f1e2 output pin. addition - ally, the receive order-wire output port will also assert the rxe1f1e2val output pin, in order to indicate that the data, residing on the rxe1f1e2 output pin is a valid order-wire byte. the receive order-wire output port will update the rxe1f1e2val, the rxe1f1e2fp and the rxe1f1e2 output pins upon the falling edge of the rxtohclk output pin. the receive order-wire circuitry that is interfaced to this output pin, and the rxe1f1e2val, the rxe1f1e2 and the rxtohclk pins is suppose to do the following; 1. it should continuously samp le and monitor the state of the rxe1f1e2val and rxe1f1e2fp output pins upon the rising edge of rxtohclk. 2. anytime the order-wire circui try samples the rxe1f1e2val and rxe1f1e2fp output pins "high", it should begin to sample and latch the contents of this output pin (as a valid order-wire bit) into the order-wire circuitry. 3. the order-wire circuitry should continue to sample and latch the con - tents of the output pin until the rxe1 f2e2val output pin is sampled "low". receive transport overhead interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 274 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ab5 rxsdcc o cmos receive - section dcc output port - output pin: this output pin, along with rxsdcc val and the rxtohclk output pins function as the receive section dcc output port of the xrt94l43. this pin outputs the content s of the section dcc (e.g., the d1, d2 and d3 bytes), within the incoming sts-12 data-stream. the receive section dcc output port will assert the rxsdccv al output pin, in order to indi - cate that the data, residing on the rxsdcc output pin is a valid section dcc byte. the receive section d cc output port will update the rxsdc - cval and the rxsdcc output pins up on the falling edge of the rxtohclk output pin. the section dcc hdlc circuitry that is interfaced to this output pin, the rxsdccval and the rxtohclk pins is suppose to do the follow - ing. 1. it should continuously sample and monitor the state of the rxsdccval output pin upon the rising edge of rxtohclk. 2. anytime the section dcc hdlc ci rcuitry samples the rxsdccval out - put pin "high", it should sample and latch the contents of this output pin (as a valid section dcc bit) into the section dcc hdlc circuitry. aa5 rxsdccval o cmos receive - section dcc output port - dcc value indicator output pin: this output pin, along with the rx tohclk and the rxsdcc output pins function as the receive section dcc output port of the xrt94l43. this output pin pulses "high" coincident to when the receive section dcc output port outputs a dcc bit via the rxsdcc output pin. this output pin is updated u pon the falling edge of rxtohclk. the section dcc hdlc controller circuitry that is interfaced to this output pin, the rxsdcc and the rxtohclk pins is suppose to do the following. 1. it should continuously sample and monitor the state of this output pin upon the rising edge of rxtohclk. 2. anytime the section dcc hdlc circuitry samples this output pin being "high", it should sample and latch the data on the rxsdcc output pin (as a valid section dcc bit) into the section dcc hdlc circuitry. w4 rxe1f1e2val o cmos receive - order wire output port - e1f1e2 value indicator output pin: this output pin, along with the rxtohclk, rxe1f1e2fp, rxe1f1e2 and rxtohclk output pins function as the receive - order wire output port of the xrt94l43. this output pin pulses "high" coincident to when the receive - order wire output port outputs the contents of an e1, f1 or e2 byte, via the rxe1f1e2 output pin. this output pin is updated u pon the falling edge of rxtohclk. the receive order-wire circuitry, that is interfaced to this output pin, the rxe1f1e2 and the rxtohclk pins is suppose to do the following. 1. it should continuously sample and monitor the state of this output pin upon the rising edge of rxtohclk. 2. anytime the receive order-wire circuitry samples this output pin being "high", it should sample and latch the data on the rxe1f1e2 output pin (as a valid order-wire bit) into the receive order-wire circuitry. receive transport overhead interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 275 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 b8 b4 aa3 ae3 c6 a1 ab3 ae4 c5 b7 ac3 af3 a8 a3 y3 ad3 rxpoh_0 rxpoh_1 rxpoh_2 rxpoh_3 rxpoh_4 rxpoh_5 rxpoh_6 rxpoh_7 rxpoh_8 rxpoh_9 rxpoh_10 rxpoh_11 rxpoh_12 rxpoh_13 rxpoh_14 rxpoh_15 o cmos receive sonet poh processor block - path overhead output port - output pin: these output pins, along with the rxpohclk_n, rxpohframe_n and rxpohvalid_n function as the receive sonet poh processor block - poh output port. these pins serially output the poh data that have been received by each of the receive sonet poh processor blocks (via the incoming sts-12 data-stream). each bit, within the po h bytes is updated (via these output pins) upon the falling edge of rxpohclk_n. as a consequence, external circuitry receiving this data, should sample this data upon the rising edge of rxpohclk_n. b9 b5 aa4 aa8 b6 c4 ab4 ae5 e7 a5 ac4 ab8 a9 d6 y4 ad4 rxpohclk_0 rxpohclk_1 rxpohclk_2 rxpohclk_3 rxpohclk_4 rxpohclk_5 rxpohclk_6 rxpohclk_7 rxpohclk_8 rxpohclk_9 rxpohclk_10 rxpohclk_11 rxpohclk_12 rxpohclk_13 rxpohclk_14 rxpohclk_15 o cmos receive sonet poh processor block - path overhead output port - clock output signal: these output pins, along with rxpoh_n, rxpohframe_n and rxpohvalid_n function as the receive sonet poh processor block - poh output port. these output pins function as the clock output signals for the receive sonet poh processor block - po h output port. the rxpoh_n, rxpohframe_n and rxpohvalid_n ou tput pins are updated upon the falling edge of this clock signal. as a consequence, the external circuitry should sample these signals upon the rising edge of this clock signal. receive transport overhead interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 276 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper b3 c3 ab1 af1 d4 f7 ac1 ac5 f5 c7 ad1 ad5 f8 e4 aa1 ae1 rxpohframe_0 rxpohframe_1 rxpohframe_2 rxpohframe_3 rxpohframe_4 rxpohframe_5 rxpohframe_6 rxpohframe_7 rxpohframe_8 rxpohframe_9 rxpohframe_10 rxpohframe_11 rxpohframe_12 rxpohframe_13 rxpohframe_14 rxpohframe_15 o cmos receive sonet poh processor block - path overhead output port - frame boundary indicator: these output pins, along with the rxpoh_n, rxpohclk_n and rxpohvalid_n output pins function as the receive sonet poh proces - sor block - path overhead output port. these output pins will pulse "high" co incident with the very first poh byte (j1), of a given sts-1 frame, is being output via the corresponding rxpoh_n output pin. receive transport overhead interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 277 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 e6 d3 ab2 af2 d5 a4 ac2 ac6 a2 c9 ad2 ac7 c8 e5 aa2 ae2 rxpohvalid_0 rxpohvalid_1 rxpohvalid_2 rxpohvalid_3 rxpohvalid_4 rxpohvalid_5 rxpohvalid_6 rxpohvalid_7 rxpohvalid_8 rxpohvalid_9 rxpohvalid_10 rxpohvalid_11 rxpohvalid_12 rxpohvalid_13 rxpohvalid_14 rxpohvalid_15 o cmos receive sonet poh processor block - path overhead output port - valid poh data indicator: these output pins, along with rxpoh_n, rxpohclk_n and rxpohframe_n function as the rece ive sonet poh processor block - path overhead output port. these output pins will toggle "high" coincident with when valid poh data is being output via the rxpoh_n output pins. this output is updated upon the falling edge of rxpohclk_n. hence, external circuitry should sample these signals upon rising edge of rxpohclk_n. aa7 lof 8khz_out o cmos receive sts-12 lof (loss of frame) indicator/8khz clock output: the function of this output pin de pends upon whether or not the 8khz clock generation feature has been enabled. 8khz clock generation feature - not enabled (nor mal mode) - the sts-12 loss of frame indicator output: this output pin indicates whether or not the receive sts-12 toh proces - sor block (within the device) is declaring the lof condition. "low" - indicates that the receive sts-12 toh processor block is not currently declaring the lof condition. "high" - indicates that the receive sts-12 toh processor block is cur - rently declaring the lof condition. 8khz clock generation feature - enabled - 8khz clock output: if this feature is enabled, the xrt94l 43 will be configured to derive and generate 8khz clock output signals, from a particular sts-1 signal that is being received via one of the 12 receive sts-1 toh/poh processor blocks. receive transport overhead interface p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 278 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper
xrt94l43 279 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 general purpose input/output p in # s ignal n ame i/o s ignal t ype d escription a19 gpio_0 extlos_0 sse_clk i/o ttl/ cmos general purpose input/output pin or external los input pin/slow- speed interface - egress - clock i/o: the function of this input pin depend s on whether or not channel 0 of the ds3/e3 framer block is enabled or whether or not the slow-speed interface is enabled. gpio_0 (ds3/e3 framer block - channel 0 is disabled). if the ds3/e3 framer block is disabl ed, then this pin will function as a general purpose input/output pin. this input pin can be configured to f unction as either an input or output pin by writing the appropriate value into bit 0 (gpio_dir_0), within the operation general purpos e input/output direction re gister - 0 (indirect address = 0x00, 0x4b), (direct address = 0x014b). when configured as an input pin, the state of this pin can be monitored by reading the state of bit 0 (gpio _0) within the oper ation general pur - pose input/output regist er - byte 0 (indirect address = 0x00, 047), (direct address = 0x0147). when configured as an output pin, the state of this pin can be controlled by writing the appropriate value into bit 0 (gpio_0) within the operation general purpose input/output regist er - byte 0 (indirect address = 0x00, 0x47), (direct address = 0x047). extlos_0 (ds3/e3 framer block - channel 0 is enabled). if the ds3/e3 framer block is enabl ed, then this pin will function as the external los input pin for channel 0. this input pin is intended to be connected to a los output pin of a ds3/e3 liu ic. if this input pin is pulled "high", then the corresponding ds3/e3 framer block will automatically declare an los condition. sse_clk (slow-speed interface - egress port is enabled): if the slow-speed interface - egress (sse) port is enabled, then this pin will function as either the sse_cl k output pin or the sse_clk input pin. if the user configures the sse port to operate in the "insert" mode, then the sse port will be configured to replace any "user-selected" egress ds3/e3 or sts-1 data-stream (wit hin the xrt94l43 device) with the data that is applied to the sse_pos and sse_neg input pins. more specifically, in the insert mode, this pin will function as the sse_clk input pin. in this case, the sse port will sample and latch the contents of the sse_pos and sse_neg input pins up on the falling edg e of this input clock signal. if the user configures the sse port to operate in the "e xtract" mode, then the sse port will output any "user-selected" egress ds3/e3 or sts-1 signal (within the xrt94l43 device) via this output port. more specifi - cally, in the "extract mode", this pi n will function as the sse_clk output pin. in this case, the sse port w ill output the data (via the sse_pos and sse_neg output pins) upon the rising edge of this output clock sig - nal.
xrt94l43 280 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper d22 gpio_1 extlos_1 ssi_clk i/o ttl/ cmos general purpose input/output pin or external los input pin/slow- speed interface - ingress - clock i/o: the function of this input pin depend s on whether or not channel 1 of the ds3/e3 framer block is enabled, or whether or not the slow speed interface is enabled. gpio_1 (ds3/e3 framer block - channel 1 is disabled). if the ds3/e3 framer block is disabl ed, then this pin will function as a general purpose input/output pin. this input pin can be configured to f unction as either an input or output pin by writing the appropriate value into bit 1 (gpio_dir_1), within the operation general purpos e input/output direction register - 0 (indirect address = 0x00, 0x4b), (direct address = 0x014b). when configured as an input pin, the state of this pin can be monitored by reading the state of bit 1 (gpio _1) within the oper ation general pur - pose input/output regist er - byte 0 (indirect address = 0x00, 047). when configured as an output pin, the state of this pin can be controlled by writing the appropriate value into bit 1 (gpio_1) within the operation general purpose input/output regist er - byte 0 (indirect address = 0x00, 0x47), (direct address = 0x0147). extlos_1 (ds3/e3 framer block - channel 1 is enabled), slow- speed interface is disabled). if the ds3/e3 framer block is enabl ed, then this pin will function as the external los input pin for channel 1. this input pin is intended to be connected to an los output pin of a ds3/e3 liu ic. if this input pin is pulled "high", then the corresponding ds3/e3 framer block will automatically declare an los condition. ssi_clk (slow-speed interface - ingress port is enabled): if the slow-speed interface -ingress (s si) port is enabled, then this pin will function as either the ssi_clk output pin or the ssi_clk input pin. if the user configures t he ssi port to operate in the "insert" mode, then the ssi port will be configured to replace any "user-selected" ingress ds3/e3 or sts-1 data-stream (wit hin the xrt94l43 device) with the data that is applied to the ssi_pos and ssi_neg input pins. more spe - cifically, in the "insert" mode, this pin will function as the "ssi_clk" input pin. in this case, the ssi port will sample and latch the contents of the ssi_pos and ssi_neg input pins upon the falling edge of this input clock signal. if the user configures the ssi port to operate in the "extract" mode, then the ssi port will output any "user-selected" ingress ds3/e3 or sts-1 signal (within the xrt94l43 device) via this output port. more specifi - cally, in the "extract mode", this pin will function as the ssi_clk output pin. in this case, the ssi port will output the data (via the ssi_pos and ssi_neg output pins) upon the rising edge of this output clock signal. general purpose input/output p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 281 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 w25 gpio_2 extlos_2 ssi_pos i/o ttl/ cmos general purpose input/output pin or external los input pin/slow- speed interface -ingress - positive data i/o: the function of this input pin depend s on whether or not channel 2 of the ds3/e3 framer block is enabled.. gpio_2 (ds3/e3 framer block - channel 2 is disabled). if the ds3/e3 framer block is disabl ed, then this pin will function as a general purpose input/output pin. th is input pin can be configured to function as either an input or output pin by writing the appropriate value into bit 2 (gpio_dir_2), within t he operation general purpose input/ output direction register - 0 (indirect address = 0x00, 0x4b), (direct address = 0x014b). when configured as an input pin, the state of this pin can be monitored by reading the state of bit 2 (gpio _2) within the oper ation general pur - pose input/output regist er - byte 0 (indirect address = 0x00, 047), (direct address = 0x0147). when configured as an output pin, the state of this pin can be controlled by writing the appropriate value into bit 2 (gpio_2) within the operation general purpose input/output regist er - byte 0 (indirect address = 0x00, 0x47), (direct address = 0x0147). extlos_2 (ds3/e3 framer block - channel 2 is enabled, slow- speed interface is disabled). if the ds3/e3 framer block is enabl ed, then this pin will function as the external los input pin for channel 2. this input pin is intended to be connected to an los output pin of a ds3/e3 liu ic. if this input pin is pulled "high", then the corresponding ds3/e3 framer block will automatically declare an los condition. ssi_pos (slow-speed interface - ingress port is enabled): if the slow-speed interface - ingress ( ssi) port is enabled, then this pin will function as either the ssi_pos output pin or the ssi_pos input pin. if the user configures t he ssi port to operate in the "insert" mode, then the ssi port will be configured to replace any "user-selected" ingress ds3/e3 or sts-1 data-stream (wit hin the xrt94l43 device) with the data that is applied to the ssi_pos and ssi_neg input pins. more spe - cifically, in the "insert" mode, this pin will function as the ssi_pos input pin. in this case, the ssi port will sample and latch the contents of this input pin (along with ssi_neg, in a dual-rail manner) upon the falling edge of the ssi_clk input clock signal. if the user configures the ssi port to operate in the "extract" mode, then the ssi port will output any "user-selected" ingress ds3/e3 or sts-1 signal (within the xrt94l43 device) via this output port. more specifi - cally, in the "extract mode", this pi n will function as the ssi_pos output pin. in this case, the ssi port will output data via this pin, along with the ssi_neg output pin (in a dual-rail manner) upon the rising edge of the ssi_clk output signal. general purpose input/output p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 282 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ac22 gpio_3 extlos_3 sse_neg i/o ttl/ cmos general purpose input/output pin or external los input pin/slow- speed interface - egress - negative data i/o: the function of this input pin depend s on whether or not channel 3 of the ds3/e3 framer block is enabled, or wheter or not the slow speed interface is enabled. gpio_3 (ds3/e3 framer block - channel 3 is disabled). if the ds3/e3 framer block is disabl ed, then this pin will function as a general purpose input/output pin. this input pin can be configured to f unction as either an input or output pin by writing the appropriate value into bit 3 (gpio_dir_3), within the operation general purpos e input/output direction register - 0 (indirect address = 0x00, 0x4b), (direct address = 0x014b). when configured as an input pin, the state of this pin can be monitored by reading the state of bit 3 (gpio _3) within the oper ation general pur - pose input/output regist er - byte 0 (indirect address = 0x00, 047), (direct address = 0x0147). when configured as an output pin, the state of this pin can be controlled by writing the appropriate value into bit 3 (gpio_3) within the operation general purpose input/output regist er - byte 0 (indirect address = 0x00, 0x47), (direct address = 0x0147). extlos_3 (ds3/e3 framer block - channel 3 is enabled, slow- speed interface is disabled). if the ds3/e3 framer block is enabl ed, then this pin will function as the external los input pin for channel 3. this input pin is intended to be connected to an los output pin of a ds3/e3 liu ic. if this input pin is pulled "high", then the corresponding ds3/e3 framer block will automatically declare an los condition. sse_neg (slow-speed interface - egress port is enabled): if the slow-speed interface - egress (sse) port is enabled, then this pin will function as either the sse_ neg output pin or the sse_neg input pin. if the user configures the sse port to operate in the "insert" mode, then the sse port will be configured to replace any "user-selected" egress ds3/e3 or sts-1 data-stream (wit hin the xrt94l43 device) with the data that is applied to the sse_pos and sse_neg input pins. more specifically, in the "ins ert" mode, this pin will function as the sse_neg input pin. in this case, the sse port will sample and latch the contents of this input pin (along with sse_pos, in a dual-rail manner) upon the falling edge of the sse_clk input clock signal. if the user configures the sse port to operate in the "e xtract" mode, then the sse port will output any "user-selected" egress ds3/e3 or sts-1 signal (within the xrt94l43 device) via this output port. more specifi - cally, in the "extract mode" this pi n will function as the sse_neg output pin. in this case, the sse port will ou tput data via this pin, along with the sse_pos output pin (in a dual-rail manner) upon the rising edge of the sse_clk output signal general purpose input/output p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 283 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 a23 gpio_4 extlos_4 i/o ttl/ cmos general purpose input/output pin or external los input pin: the function of this input pin depend s on whether or not channel 4 of the ds3/e3 framer block is enabled. gpio_4 (ds3/e3 framer block - channel 4 is disabled). if the ds3/e3 framer block is disabl ed, then this pin will function as a general purpose input/output pin. th is input pin can be configured to function as either an input or output pin by writing the appropriate value into bit 4 (gpio_dir_4), within t he operation general purpose input/ output direction register - 0 (indirect address = 0x00, 0x4b), (direct address = 0x014b). when configured as an input pin, the state of this pin can be monitored by reading the state of bit 4 (gpio _4) within the oper ation general pur - pose input/output regist er - byte 0 (indirect address = 0x00, 047), (direct address = 0x0147). when configured as an output pin, the state of this pin can be controlled by writing the appropriate value into bit 4 (gpio_4) within the operation general purpose input/output regist er - byte 0 (indirect address = 0x00, 0x47), (direct address = 0x0147). extlos_4 (ds3/e3 framer block - channel 4 is enabled). if the ds3/e3 framer block is enabl ed, then this pin will function as the external los input pin for channel 4. this input pin is intended to be connected to an los output pin of a ds3/e3 liu ic. if this input pin is pulled "high", then the corresponding ds3/e3 framer block will automatically declare an los condition. f24 gpio_5 extlos_5 i/o ttl/ cmos general purpose input/output pin or external los input pin: the function of this input pin depend s on whether or not channel 5 of the ds3/e3 framer block is enabled. gpio_5 (ds3/e3 framer block - channel 5 is disabled). if the ds3/e3 framer block is disabl ed, then this pin will function as a general purpose input/output pin. th is input pin can be configured to function as either an input or output pin by writing the appropriate value into bit 5 (gpio_dir_5), within t he operation general purpose input/ output direction register - 0 (indirect address = 0x00, 0x4b), (direct address = 0x014b). when configured as an input pin, the state of this pin can be monitored by reading the state of bit 5 (gpio _5) within the oper ation general pur - pose input/output regist er - byte 0 (indirect address = 0x00, 047), (direct address = 0x0147). when configured as an output pin, the state of this pin can be controlled by writing the appropriate value into bit 5 (gpio_5) within the operation general purpose input/output regist er - byte 0 (indirect address = 0x00, 0x47), (direct address = 0x0147). extlos_5 (ds3/e3 framer block - channel 5 is enabled). if the ds3/e3 framer block is enabl ed, then this pin will function as the external los input pin for channel 1. this input pin is intended to be connected to an los output pin of a ds3/e3 liu ic. if this input pin is pulled "high", then the corresponding ds3/e3 framer block will automatically declare an los condition. general purpose input/output p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 284 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper w21 gpio_6 extlos_6 i/o ttl/ cmos general purpose input/output pin or external los input pin: the function of this input pin depend s on whether or not channel 6 of the ds3/e3 framer block is enabled. gpio_6 (ds3/e3 framer block - channel 6 is disabled). if the ds3/e3 framer block is disabl ed, then this pin will function as a general purpose input/output pin. th is input pin can be configured to function as either an input or output pin by writing the appropriate value into bit 6 (gpio_dir_6), within t he operation general purpose input/ output direction register - 0 (indirect address = 0x00, 0x4b), (direct address = 0x014b). when configured as an input pin, the state of this pin can be monitored by reading the state of bit 6 (gpio _6) within the oper ation general pur - pose input/output regist er - byte 0 (indirect address = 0x00, 047), (direct address = 0x0147). when configured as an output pin, the state of this pin can be controlled by writing the appropriate value into bit 6 (gpio_6) within the operation general purpose input/output regist er - byte 0 (indirect address = 0x00, 0x47), (direct address = 0x0147). extlos_6 (ds3/e3 framer block - channel 6 is enabled). if the ds3/e3 framer block is enabl ed, then this pin will function as the external los input pin for channel 6. this input pin is intended to be connected to an los output pin of a ds3/e3 liu ic. if this input pin is pulled "high", then the corresponding ds3/e3 framer block will automatically declare an los condition. ae22 gpio_7 extlos_7 i/o ttl/ cmos general purpose input/output pin or external los input pin: the function of this input pin depend s on whether or not channel 7 of the ds3/e3 framer block is enabled. gpio_7 (ds3/e3 framer block - channel 7 is disabled). if the ds3/e3 framer block is disabl ed, then this pin will function as a general purpose input/output pin. th is input pin can be configured to function as either an input or output pin by writing the appropriate value into bit 7 (gpio_dir_7), within t he operation general purpose input/ output direction register - 0 (indirect address = 0x00, 0x4b), (direct address = 0x014b). when configured as an input pin, the state of this pin can be monitored by reading the state of bit 7 (gpio _7) within the oper ation general pur - pose input/output regist er - byte 0 (indirect address = 0x00, 047), (direct address = 0x0147). when configured as an output pin, the state of this pin can be controlled by writing the appropriate value into bit 7 (gpio_7) within the operation general purpose input/output regist er - byte 0 (indirect address = 0x00, 0x47), (direct address = 0x0147). extlos_7 (ds3/e3 framer block - channel 7 is enabled). if the ds3/e3 framer block is enabl ed, then this pin will function as the external los input pin for channel 7. this input pin is intended to be connected to an los output pin of a ds3/e3 liu ic. if this input pin is pulled "high", then the corresponding ds3/e3 framer block will automatically declare an los condition. general purpose input/output p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 285 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 a25 gpio_8 extlos_8 i/o ttl/ cmos general purpose input/output pin or external los input pin: the function of this input pin depend s on whether or not channel 8 of the ds3/e3 framer block is enabled. gpio_8 (ds3/e3 framer block - channel 8 is disabled). if the ds3/e3 framer block is disabl ed, then this pin will function as a general purpose input/output pin. th is input pin can be configured to function as either an input or output pin by writing the appropriate value into bit 0 (gpio_dir_8), within t he operation general purpose input/ output direction register - 1 (indirect address = 0x00, 0x4a), (direct address = 0x014a). when configured as an input pin, the state of this pin can be monitored by reading the state of bit 0 (gpio _8) within the oper ation general pur - pose input/output regist er - byte 1 (indirect address = 0x00, 046), (direct address = 0x0146). when configured as an output pin, the state of this pin can be controlled by writing the appropriate value into bit 0 (gpio_8) within the operation general purpose input/output regist er - byte 1 (indirect address = 0x00, 0x46), (direct address = 0x0146). extlos_8 (ds3/e3 framer block - channel 8 is enabled). if the ds3/e3 framer block is enabl ed, then this pin will function as the external los input pin for channel 8. this input pin is intended to be connected to an los output pin of a ds3/e3 liu ic. if this input pin is pulled "high", then the corresponding ds3/e3 framer block will automatically declare an los condition. h24 gpio_9 extlos_9 i/o ttl/ cmos general purpose input/output pi n or external los input pin: the function of this input pin depend s on whether or not channel 9 of the ds3/e3 framer block is enabled. gpio_9 (ds3/e3 framer block - channel 8 is disabled). if the ds3/e3 framer block is disabl ed, then this pin will function as a general purpose input/output pin. th is input pin can be configured to function as either an input or output pin by writing the appropriate value into bit 1 (gpio_dir_9), within t he operation general purpose input/ output direction register - 1 (indirect address = 0x00, 0x4a), (direct address = 0x014a). when configured as an input pin, the state of this pin can be monitored by reading the state of bit 1 (gpio _9) within the oper ation general pur - pose input/output regist er - byte 1 (indirect address = 0x00, 046), (direct address = 0x014a). when configured as an output pin, the state of this pin can be controlled by writing the appropriate value into bit 1 (gpio_9) within the operation general purpose input/output regist er - byte 1 (indirect address = 0x00, 0x46), (direct address = 0x0146). extlos_9 (ds3/e3 framer block - channel 9 is enabled). if the ds3/e3 framer block is enabl ed, then this pin will function as the external los input pin for channel 9. this input pin is intended to be connected to an los output pin of a ds3/e3 liu ic. if this input pin is pulled "high", then the corresponding ds3/e3 framer block will automatically declare an los condition. general purpose input/output p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 286 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ab23 gpio_10 extlos_10 i/o ttl/ cmos general purpose input/output pin or external los input pin: the function of this input pin depends on whether or not channel 10 of the ds3/e3 framer block is enabled. gpio_10 (ds3/e3 framer block - channel 10 is disabled). if the ds3/e3 framer block is disabl ed, then this pin will function as a general purpose input/output pin. th is input pin can be configured to function as either an input or output pin by writing the appropriate value into bit 2 (gpio_dir_10), within the operation general purpose input/ output direction register - 1 (indirect address = 0x00, 0x4a), (direct address = 0x014a). when configured as an input pin, the state of this pin can be monitored by reading the state of bit 2 (gpi o_10) within the operation general purpose input/output register - by te 1 (indirect address = 0x00, 046), (direct address = 0x0146). when configured as an output pin, the state of this pin can be controlled by writing the appropriate value into bit 2 (gpio_10) within the opera - tion general purpose input/output register - byte 1 (indirect address = 0x00, 0x46), (direct address = 0x0146). extlos_10 (ds3/e3 framer block - channel 10 is enabled). if the ds3/e3 framer block is enabl ed, then this pin will function as the external los input pin for channel 10. this input pin is intended to be connected to an los output pin of a ds3/e3 liu ic. if this input pin is pulled "high", then the corresponding ds3/e3 framer block will automatically declare an los condition. ad15 gpio_11 extlos_11 i/o ttl/ cmos general purpose input/output pin or external los input pin: the function of this input pin depends on whether or not channel 11 of the ds3/e3 framer block is enabled. gpio_11 (ds3/e3 framer block - channel 11 is disabled). if the ds3/e3 framer block is disabl ed, then this pin will function as a general purpose input/output pin. th is input pin can be configured to function as either an input or output pin by writing the appropriate value into bit 3 (gpio_dir_11), within th e operation general purpose input/ output direction register - 1 (indirect address = 0x00, 0x4a), (direct address = 0x014a). when configured as an input pin, the state of this pin can be monitored by reading the state of bit 3 (gpi o_11) within the operation general purpose input/output register - by te 1 (indirect address = 0x00, 046), (direct address = 0x0146). when configured as an output pin, the state of this pin can be controlled by writing the appropriate value into bit 3 (gpio_11) within the opera - tion general purpose input/output register - byte 1 (indirect address = 0x00, 0x46), (direct address = 0x0146). extlos_11 (ds3/e3 framer block - channel 11 is enabled). if the ds3/e3 framer block is enabl ed, then this pin will function as the external los input pin for channel 11. this input pin is intended to be connected to an los output pin of a ds3/e3 liu ic. if this input pin is pulled "high", then the corresponding ds3/e3 framer block will automatically declare an los condition. general purpose input/output p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 287 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 clock inputs p in # s ignal n ame i/o s ignal t ype d escription p23 refclk34 i ttl e3 reference clock inpu t for the jitter attenuat or within the ds3/e3 mapper block: apply a signal with a frequency of 34.36820ppm to this input pin. this input pin functions as the timing reference for the ds3/e3/sts-1 jitter attenuator (within the ds3/e3 mapper block) for e3 applications. p24 refclk51 i ttl sts-1 reference clock input for the jitter attenuator within the ds3/ e3 mapper block: the user is expected to apply a signal with a frequency of 51.84mhz20ppm to this input pin. th is input pin functions as the timing reference for the ds3/e3/sts-1 jitte r attenuator (within the ds3/e3 map - per block) for sts-1 applications. p25 refclk45 i ttl ds3 reference clock input for the jitt er attenuator wi thin the ds3/e3 mapper block: apply a signal with a frequency of 44.73620ppm to this input pin. this input pin functions as the timing reference for the ds3/e3/sts-1 jitter attenuator (within the ds3/e3 map per block) for ds3 applications. boundary scan p in # s ignal n ame i/o s ignal t ype d escription b2 tdo o c2 tdi i b1 trst i g5 tck i h6 tms i miscellaneous pins p in # s ignal n ame i/o s ignal t ype d escription l21 te s t m o d e i test mode input pin: tie this input pin "low" for normal operation.
xrt94l43 288 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper power supply pins p in # s ignal n ame i/o s ignal t ype d escription vdd = 3.3v n6 n5 p3 r3 analog vdd pins (transmitter) _ transmitter analog power supply voltage = 3.3v nominal p4 analog vdd pins (pll) pll analog power supply voltage = 3.3v nominal l1 analog vdd pins (receiver) receiver analog power supply voltage = 3.3v nominal u6 r15 r16 p15 p16 n15 n16 m15 m16 l15 l16 aa10 aa11 aa9 f10 f11 f9 k21 digital vdd digital power supply voltage = 3.3v nominal vdd (2.5v) p6 m4 n21 n26 p22 analog vdd pins (pll) pll analog power supply voltage = 2.5 v nominal r6 analog vdd pins (transmitter) transmitter analog power supply voltage = 2.5 v nominal
xrt94l43 289 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 l6 analog vdd pins (receiver) receiver analog power supply voltage = 2.5 v nominal u21 r11 r12 p11 p12 n11 n12 m11 m12 l11 l12 k6 f16 f17 f18 aa16 aa17 aa18 digital vdd digital power supply voltage = 2.5 v nominal power supply pins p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 290 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper ground p in # s ignal n ame i/o s ignal t ype d escription y6 y21 t11 t12 t13 t14 t15 t16 r13 r14 p13 p14 n13 n14 m13 m14 l13 l14 g6 g21 f6 f21 f13 f14 aa6 aa21 aa13 aa14 gnd _ ground n3 n4 m3 r5 p5 t6 l2 m6 m21 n24 n25 n22 n23 p21 analog ground no connects m23 nc
xrt94l43 291 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 m26 nc t5 nc ground p in #s ignal n ame i/o s ignal t ype d escription
xrt94l43 292 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper dc electrical characteristics dc characteristics for ttl input/cmos output applies to all ttl-level input and cmos level output pins - ambient temperature = 25c s ymbol p arameter m in m ax u nits c ondition vddq i/o supply voltage 3.135 3.465 v vih high-level input voltage 2.0 vdd+0.3 v vout > voh(min) vil low-level input voltage -0.3 0.3*vdd v vout < vol(max) voh high-level output voltage 1.9 v vdd = min vin = vih ioh = -2ma vol low-level output voltage 0.6 v vdd = min vin = vil iol = 2ma ii input current 15 a vdd = max vin = vdd or gnd dc characteristics for lvpecl i/o applies to all lvpecl input and output pins s ymbol p arameter m in m ax u nits c ondition vih high-level input voltage vdd+0.4 v vil low-level input voltage -0.4 v vicm input common mode voltage 1.0 vdd v vindiff differential input voltage 0.2 v voh high-level output voltage vdd-1.08 vdd-0.88 v vol low-level output voltage vdd-1.88 vdd-1.62 v voutdiff differential output voltage 1.18 2.12 v
xrt94l43 293 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ac electrical characteristics 1.0 microprocessor interface ti ming for revision d silicon 1.1 microprocessor interface timing - asynchronous intel mode n ote : the values for t 0 through t 7 , within this figure can be found in table 1 . n ote : the values for t 0 through t 7 , within this figure can be found in table 1 . f igure 5. a synchronous m ode 1 - i ntel t ype p rogrammed i/o t iming (w rite c ycle ) f igure 6. a synchronous m ode 1 - i ntel t ype p rogrammed i/o t iming (r ead c ycle ) address data t5 cs ale_as a[6:0] d[7:0] rd_ds wr_r/w t 0 t 1 t 3 t 4 t 2 address data cs ale_as a[6:0] d[7:0] rd_ds wr_r/w rdy_dtack t 2 t 7 t 6 t 1 t 0 t 5
xrt94l43 294 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper n ote : test conditions: ta = 25c, vcc = 3.3v5 % and 2.5v5%, unless otherwise specified. 1.2 microprocessor interface timing - asynchronous motorola (68k) mode n ote : the values for t 0 through t 7 can be found in table 2 . t able 1: t iming i nformation for the m icroprocessor i nterface , when configured to operate in the i ntel a synchronous m ode t iming d escription m in . t yp . m ax . t 0 address setup time to pale low 6 - - t 1 address hold time to pale low 6 - - t 2 prd_l, pwr_l pulse width 320 - - t 3 data setup time to pwr_l low 0 - - t 4 data hold time to pwr_l high 0 - - t 5 pale low to prd_l, pwr_l low 5 - - t 6 data invalid from prd_l high 7 - - t 7 data valid from prdy_l low - - 0 f igure 7. a synchronous m ode 2 - m otorola 68k p rogrammed i/o t iming (w rite c ycle ) address data t 0 cs ale_as a[6:0] d[7:0] rd_ds wr_r/w rdy_dtack t 2 t 3 t 4 t 1
xrt94l43 295 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 n ote : the values for t 0 through t 7 can be found in table 2 . n ote : test conditions: ta = 25c, vcc = 3.3v5 % and 2.5v5%, unless otherwise specified. f igure 8. a synchronous m ode 2 - m otorola 68k p rogrammed i/o t iming (r ead c ycle ) t able 2: t iming i nformation for the m icroprocessor i nterface when configured to operate in the m otorola (68k) a synchronous m ode t iming d escription m in . t yp . m ax t 0 address setup time to pale low 6 - - t 1 address hold time to pale high 6 - - t 2 data setup time to pds_l low 0 - - t 3 data hold time to pds_l low 160 - - t 4 pds_l high to prdy_l high (write cycle) - - 16 t 5 prdy_l low to data valid - - 15 t 6 pds_l high to prdy_l high (read cycle) - - 16 t 7 prdy_l high to data invalid 3 - - data cs ale_as a[6:0] d[7:0] rd_ds wr_r/w rdy_dtack t 6 t 7 address t 0 t 1 t 5
xrt94l43 296 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper 1.3 microprocessor interface timing - power pc 403 synchronous mode n ote : the value for t 0 through t 12 can be found in table 3 . f igure 9. s ynchronous m ode 3 - ibm p ower pc 403 i nterface t iming (w rite c ycle ) pclk pcs_l pa[7:0] pd[7:0] prdy prw_l poe_l t 0 address data pwe_l t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9
xrt94l43 297 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 n ote : the value for t 0 through t 12 can be found in table 3 . n ote : test conditions: ta = 25c, vcc = 3.3v5 % and 2.5v5%, unless otherwise specified. f igure 10. s ynchronous m ode 3 - ibm p ower pc 403 i nterface t iming (r ead c ycle ) t able 3: t iming i nformation for the m icroprocessor i nterface , when configured to operate in the ibm p ower pc403 m ode t iming d escription m in . t yp . m ax . t 0 pcs_l low to clock high 10 - - t 1 prw_l low to clock high 9 - - t 2 address setup time 9 - - t 3 address hold time 5 - - t 4 data setup time (write cycle) 9 - - t 5 data hold time (write cycle) 0 - - t 6 pwe_l low to clock high 6 - - t 7 clock high to pwe_l high 6 - - t 8 clock high to prdy high - - 10 t 9 clock high to prdy low - - 10 t 10 clock high to data valid (read cycle) - - 11 t 11 clock high to poe_l low 11 - - t 12 clock high to poe_l high 11 - - pclk pcs_l pa[7:0] pd[7:0] prdy prw_l poe_l address pwe_l data t 10 t 11 t 12
xrt94l43 298 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper 1.4 microprocessor interfac e timing - id t3051/52 mode n ote : the values for t 0 through t 11 can be found in table 4 . f igure 11. s ynchronous m ode 4 - idt3051/52 i nterface t iming (w rite c ycle ) pclk pcs_l pa[7:0] pd[7:0] prdy_l pwr_l prd_l t 0 data pdben_l pale address t 1 t 2 t 3 t 4 t 5 t 6
xrt94l43 299 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 n ote : the values for t 0 through t 11 can be found in table 4 . n ote : test conditions: ta = 25c, vcc = 3.3v5 % and 2.5v5%, unless otherwise specified. 2.0 sts-12/stm-4 telecom bus interface timing information f igure 12. s ynchronous m ode 4 - idt3051/52 i nterface t iming (r ead c ycle ) t able 4: t iming i nformation for the m icroprocessor i nterface , when configured to operate in the idt3051/52 m ode t iming d escription m in . t yp . m ax . t 0 pcs_l low to clock high 6 - - t 1 pale high to clock high 1 - - t 2 clock high to pale low 6 - - t 3 data setup time (write cycle) - - n/n t 4 data hold time (write cycle) - - n/n t 5 clock high to prdy_l low - - 11 t 6 clock high to pwr_l high 6 - - t 7 clock high to data valid (read cycle) - - n/n t 8 clock high to prdy_l high - - 11 t 9 prdy_l high to data invalid 0 - - t 10 clock high to prd_l high 11 - - t 11 clock high to pdben_l high 10 - - t 7 t 8 t 9 pclk pcs_l pa[7:0] pd[7:0] prdy_l pwr_l prd_l t 5 pdben_l pale address t 10 t 11 data
xrt94l43 300 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper 2.1 sts-12/stm-4 telecom bus interface timing information this section presents the timing requirements for the st s-12/stm-4 telecom bus interface. in particular this section indicates the following. a. identifies which edge of txa_clk in which t he txa_d[7:0], txa_pl, tx a_c1j1, txa_alarm and txa_dp output pins are updated on. b. the clock to output delays (from the rising edge of txa_clk to the instant that the txa_d[7:0], txa_pl, txa_c1j1, txa_alarm and txa_dp output pins are updated. c. the set-up and hold-time requirements of txsbfp with respect to the refclk input. d. identifies which edge of rxd_clk that the rxd_d[7:0], rxd_pl, rxd_c1j1, rxd_alarm and rxd_dp input pins are sampled on. e. the set-up time requirements (from an update in the rxd_d[7:0], rxd_pl, rxd_c1j1, rxd_alarm and rxd_dp input signals to the rising edge of rxd_clk). f. the hold-time requirements (from the rising edge of rxd_clk to a change in the rxd_d[7:0], rxd_pl, rxd_c1j1, rxd_alarm and rxd_dp input signals) 2.2 the transmit sts-12/stm-4 telecom bus interface timing in the transmit sts-12/stm-4 telecom bus interface, a ll of the signals (which are output via this bus interface) are updated upon the rising ed ge of txa_clk (77.76mhz clock signal). figure 13 and figure 14 presents an illustration of the waveforms of the signal s that will be output via the transmit sts-12/stm-4 telecom bus interface, as well as the timing parameter (t1). n ote : the value for t 1 can be found in table 5 . f igure 13. w aveforms of the s ignals that are output via the t ransmit sts-12/stm-4 t elecom b us i nterface t 1 txa_clk txa_d[7:0] txa_pl txa_c1j1 a2 c1 c1 j1 data j1
xrt94l43 301 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 the txsbfp input signal is sampled upon the rising edge of txa_clk by the transmit sts-12/stm-4 telecom bus interface circuitr y, as illustrated below in figure 14 . n ote : the value for t 4 , t 5 , t 5a and t 5b can be found in table 5 . table 5 presents information on the timing parameters for the transmit sts-12/stm-4 telecom bus interface. 2.3 the receive sts-12/stm-4 telecom bus interface timing in the receive sts-12/stm-4 telecom bus interface, all of the signals (which are input via this bus interface) are sampled upon the rising edge of rxd_clk (77.76mhz clock signal). figure 15 presents an illustration of the waveforms and the timi ng parameters (t2 and t3 ) of the signals that will be received by the receive sts- 12/stm-4 teleco m bus interface. f igure 14. t iming relationships between the t x sbfp input pin and the t x a_clk output pin within the t ransmit sts-12/stm-4 t elecom b us i nterface t able 5: t iming i nformation for the t ransmit sts-12/stm-4 t elecom b us i nterface s ymbol d escription m in . t yp . m ax . t 1 rising edge of txa_clk to updates in txa_d[7:0], txa_pl, txa_c1j1 and txa_dp 3.7ns 9.5ns t 4 txsbfp set-up time to rising edge of txa_clk 8.5ns t 5 txa_clk rising edge to txsbfp hold time 0ns t 5a txsbfp set-up time to rising edge of refclk 5ns t 5b rising edge of refclk to txsbfp hold time 0ns t 4 txa _d[7:0] txsbfp data a1 a1 data data data txa _clk t 5 refclk t 5a t 5b
xrt94l43 302 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper n ote : the value for t 2 and t 3 can be found in table 6 . table 6 presents information on the timing parameters for the receive sts-12/stm-4 telecom bus interface. f igure 15. w aveforms of the s ignals that are i nput via the r eceive sts-12/stm-4 t elecom b us i nter - face t able 6: t iming i nformation for the r eceive sts-12/stm-4 t elecom b us i nterface s ymbol d escription m in . t yp . m ax . t 2 rxd_d[7:0], rxd_pl, rxd_c1j1, rxd_alarm and rxd_dp to rising edge of rxd_clk set-up time requirements 3 ns t 3 rising edge of rxd_clk to rxd_d[7:0], rxd_pl, rxd_c1j1, rxd_alarm and rxd_dp hold time requirements 0 ns rxd_clk rxd_d[7:0] rxd_pl rxd_c1j1 a2 c1 c1 j1 data data t 2 t 3
xrt94l43 303 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 3.0 sts-12/stm-4 pecl interface timing information 3.1 the receive sts-12/stm-4 pecl interface timing the receive sts-12/stm-4 pecl interface block samp les the incoming sts-12/stm-4 signal (which is present on the rxl_data_p/rxl_data_n input pins) up on the rising edge of the rxl_clkl_p/rxl_clkl_n input clock signal. n ote : table 7 presents information on the timing paramete rs for the receive sts-12/stm-4 pecl interface n ote : these timing requirements apply to both the primar y and the redundant receive sts-12/stm-4 pecl interface blocks. f igure 16. w aveforms of the s ignals that are i nput via the r eceive sts-12/stm-4 pecl i nterface t able 7: t iming i nformation for the r eceive sts-12/stm-4 pecl i nterface s ymbol d escription m in . t yp . m ax . t 6 rxl_data to rising edge of rxl_clkl set-up time require - ments 200ps t 7 rising edge of rxl_clkl to rxl_data hold time require - ments 200ps rxl _clkl_p rxl _clkl_n rxl _data_n rxl _data_p t 6 t 7
xrt94l43 304 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper 3.2 the transmit sts-12/st m-4 pecl interface block the outbound sts-12/stm-4 data (from the transmit st s-12/stm-4 pecl interface block) is updated upon the rising edge of txlclko_p/txlclko_n via the txldata_p/txldata_n output pins. table 8 presents information on the timing parameter for the transmit sts-12/stm-4 pecl interface n ote : these timing requirements apply to both the primary a nd the redundant transmit sts-12/stm-4 pecl interface block. 4.0 ds3/e3/sts-1 liu interf ace timing information 4.1 ingress ds3/e3/sts-1 interface timing the user should be aware of the following things about the ingress ds3/e3/s ts-1 interface timing. a. if a given channel is configured to operate in the ds3/e3 mode, then the ds3/e3 framer block can be configured to sample the ds3/e3/sts_1_data_in and the ds3/e3/sts_1_neg_in input pins upon either the rising or falling e dge of ds3/e3/sts_1_clock. b. if a given channel is configured to operate in the sts-1/stm-0 mode, then the receive sts-1 toh pro - cessor block will be operating in the single-rail mode (e.g., the receive sts-1 toh processor block will only sample the ds3/e3/sts_1_data_in input signal . it will not sample the ds3/e3/sts_1_neg_in input signal. c. further, if a given channel is configured to oper ate in the sts-1/stm-0 mode, then the receive sts-1 toh processor block can only be configured to sa mple the ds3/e3/sts_1_data_in input signal, upon the rising edge of ds3/e3/sts_1_clock_i n. the receive sts-1 toh processor block can - not be configured to sample the ds3/e3/sts_1_data_in input signal upon the falling edge of ds3/ e3/sts_1_clock_in. f igure 17. w aveforms of the t ransmit sts-12/stm-4 pecl i nterface s ignals t able 8: t iming i nformation for the t ransmit sts-12/stm-4 pecl i nterface s ymbol d escription m in . t yp . m ax . t 8 rising edge of txlclko to txldata out delay 600ps 800ps 1ns txlclko_p txlclko_n txldata_n txldata_p t 8
xrt94l43 305 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 the timing diagram for the ingress ds3/e3/sts-1 interface is presented below in figure 18 . n ote : the values for t 9 and t 10 are presented in table 9 , table 10 and table 11 . 4.2 ingress timing for ds3/e3 applications table 9 presents information on the timing parameters for the ds3/e3/sts-1 liu interface signals (in the ingress direction) for ds3/e3 applications, and when th e ds3/e3 framer block has been configured to sample the ds3/e3/sts_1_data_in and ds3/e3/sts_1_neg_ in signals upon the rising edge of ds3/e3/ sts_1_clock_in. table 10 presents information on the timing parameters for the ds3/e3/sts-1 liu interface signals (in the ingress direction) for ds3/e3 applications, and when th e ds3/e3 framer block has been configured to sample the ds3/e3/sts_1_data_in and ds3/e3/sts_1_neg _in signals upon the falling edge of ds3/e3/ sts_1_clock_in. f igure 18. w aveforms of the ds3/e3/sts-1 signals that are input to the ds3/e3/sts-1 liu interface in the ingress direction t able 9: t iming information for the ingress ds3/ e 3/sts-1 liu interface for ds3/e3 applications when the ds3/e3 framer block has been configured to sample the ds3/e3/sts_1_data_in and ds3/e3/ sts_1_neg_in input pins upon the rising edge of ds3/e3/sts_1_clock_in s ymbol d escription m in . t yp . m ax . t 9 ds3/e3/sts_1_data_in and ds3/e3/sts_1_neg_in to rising edge of ds3/e3/sts_1_clock_in set-up time requirements 7ns t 10 rising edge of ds3/e3/sts_1_clock_in to ds3/e3/ sts_1_data_in and ds3/e3/sts_1_neg_in hold time requirements 0ns ds3/e3/sts_1_data_in ds3/e3/sts_1_clock_in ds3/e3/sts_1_neg_in t 9 t 10
xrt94l43 306 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper 4.3 ingress timing for sts-1/stm-0 applications table 11 presents information on the timing parameters for the ds3/e3/sts-1 liu interface signals (in the ingress direction) for sts-1/stm-0 applications. 4.4 the egress ds3/e3/sts-1 interface timing the user should be aware of the followings things about the egress ds3/e3/sts-1 interface timing. a. if a given channel is configured to operate in the ds3/e3 mode, then the ds3/e3 framer block can be configured to output the outbound ds3/e3 data (via the ds3/e3/sts_1_data_out and ds3/e3/ sts_1_neg_out output pins ) upon either the risi ng or falling edge of ds3/e3/sts_1_clock_out. b. if a given channel is configured to operate in the sts-1/stm-0 mode, then the transmit sts-1 toh processor block will be operating in the single-rail mode (e.g., the transmit sts-1 toh processor block will output all outbou nd sts-1/stm-0 data via the ds3/e3 /sts_1_data_out output pin. no data will be output via the ds3/ e3/sts_1_neg_out output pin). c. further, if a given channel is configured to oper ate in the sts-1/stm-0 mode, then the transmit sts-1 toh processor block can only be configured to output the outbound sts-1/stm-0 data (via the ds3/ e3/sts_1_data_out pin) upon the risi ng edge of ds3/e3/sts_1_clock_out. t able 10: t iming i nformation for the i ngress ds3/e3/sts-1 liu i nterface for ds3/e3 a pplications and when the ds3/e3 f ramer b lock has been configured to sample the ds3/e3/sts_1_data_in and ds3/e3/sts_1_neg_in input pins upon the falling edge of ds3/e3/sts_1_clock_in s ymbol d escription m in . t yp . m ax . t 9 ds3/e3/sts_1_data_in and ds3/e3/sts_1_neg_in to falling edge of ds3/e3/sts_1_clock_in set-up time requirements 7ns t 10 falling edge of ds3/e3/sts_1_clock_in to ds3/e3/ sts_1_data_in and ds3/e3/sts_1_neg_in hold time requirements 0ns t able 11: t iming i nformation for the i ngress ds3/e3/sts-1 liu i nterface for sts-1/stm-0 a pplications s ymbol d escription m in . t yp . m ax . t 9 ds3/e3/sts_1_data_in to rising edge of ds3/e3/ sts_1_clock_in set-up time requirements 4ns t 10 rising edge of ds3/e3/sts_1_clk_in to ds3/e3/ sts_1_data_in and ds3/e3/sts_1_clock_in hold time requirements 0ns
xrt94l43 307 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 the timing diagram for the egress ds3/e3/sts-1 interface is presented below in figure 19 . n ote : the value for t 11 is presented in table 12 , table 13 and table 14 . 4.5 egress timing for ds3/e3 applications table 12 presents information on the timing parameters fo r the ds3/e3/sts-1 liu interface signals (in the egress direction) for ds3/e3 applications and when the ds3/e3 framer block has been configured to output the outbound ds3/e3 data (via the ds3/e3/sts_1_d ata_out and ds3/e3/sts_1_neg_out signal upon the rising edge of ds3/e3/sts_1_clock_out. table 13 presents information on the timing parameters fo r the ds3/e3/sts-1 liu interface signal (in the egress direction) for ds3/e3 applications and when the ds3/e3 framer block has been configured to output the outbound ds3/e3 data (via the ds3/e3/sts_1_d ata_out and ds3/e3/sts_1_neg_out signals upon the falling edge of ds3/e3/sts_1_clock_out. f igure 19. w aveforms of the ds3/e3/sts-1 signals that are output from the ds3/e3/sts-1 liu i nterface ( in the r eceive /e gress d irection ) t able 12: t iming i nformation for the e gress ds3/e3/sts-1 liu i nterface for ds3/e3 a pplications and when the ds3/e3 f ramer b lock has been configured to output the outbound ds3/e3 data ( via the ds3/e3/sts_1_data_out and ds3/e3/sts_1_neg_out output pins ) upon the rising edge of ds3/e3/ sts_1_clock_out s ymbol d escription m in . t yp . m ax . t 11 rising edge of ds3/e3/sts_1_clk_out to ds3/e3/ sts_1_data_out & ds3/e3/s ts_1_neg_out output delay 0ns 4ns t able 13: t iming i nformation for the e gress ds3/e3/sts-1 liu i nterface for ds3/e3 a pplications and when the ds3/e3 f ramer b lock has been configured to output the outbound ds3/e3 data ( via the ds3/e3/sts_1_data_out and ds3/e3/sts_1_neg_out output pins ) upon the falling edge of ds3/ e3/sts_1_clock_out s ymbol d escription m in . t yp . m ax . t 11 rising edge of ds3/e3/sts_1_clk_out to ds3/ e3/sts_1_data_out & ds3/e3/ sts_1_neg_out output delay 0ns 4ns ds3/e3/sts_1_data_out ds3/e3/sts_1_clock_out ds3/e3/sts_1_neg_out t 11
xrt94l43 308 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper 4.6 egress timing for st s-1/stm-0 applications table 14 presents information on the timing parameters for the ds3/e3/sts-1 liu interface signals (in the egress direction) for sts- 1/stm-0 applications. 5.0 sts-3/stm-1 telecom bus in terface timing information 5.1 sts-3/stm-1 telecom bus interface timing information this section presents the timing requirements for the st s-3/stm-1 telecom bus interface. in particular this section indicates the following. a. identifies which edge of rxd_clk in which th e rxd_d[7:0], rxd_pl, rxd_c1j1, rxd_alarm and rxd_dp output pins are updated on. b. the clock to output delays (fro m the rising edge of rxd_clk to the instant that the rxd_d[7:0], rxd_pl, rxd_c1j1, rxd_alarm and rxd_dp output pins are updated. c. identifies which edge of txa_clk that the txa_d[ 7:0], txa_pl, txa_c1j1 and txa_dp input pins are sampled on. d. the set-up time requirements (from an update in the txa_d[7:0], txa_pl, txa_c1j1, txa_alarm and txa_dp input signals to the rising edge of txa_clk). e. the hold-time requirements (from the rising edge of txa_clk to a change in the txa_d[7:0], txa_pl, txa_c1j1, txa_alarm and txa_dp input signals) in contrast to the names that are given to the transm it and receive sts-3/stm-1 telecom bus interface, the transmit sts-3/stm-1 telecom bus inte rface will have the responsibility of receiving (in lieu of transmitting) sts-3/stm-1 data from some remote entity over a telecom bus interface that is clocked at 19.44mhz. likewise, the receive sts-3/stm-1 tele com bus interface will have the responsibility of tr ansmitting (in lieu of receiving) sts-3/stm-1 data to some remote entity ov er a telecom bus interface that is also clocked at 19.44mhz. 5.2 the receive sts-3/stm-1 telecom bus interface timing in the receive sts-3/stm-1 telecom bus interface, all of the signals (which are output via this bus interface) are updated upon the rising edge of rxd_clk (19.44mhz clock signal). t able 14: t iming i nformation for the e gress ds3/e3/sts-1 liu i nterface for sts-1/stm-0 a pplications s ymbol d escription m in . t yp . m ax . t 11 rising edge of ds3/e3/sts_1_clk_out to ds3/ e3/sts_1_data_out output delay 0ns 3ns
xrt94l43 309 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 figure 20 and figure 21 presents an illustration of the waveforms of the signal s that will be output via the receive sts-3/stm-1 telecom bus interface along with th e timing parameter (t12). n ote : the value for t 12 can be found in table 15 . table 15 presents information on the timing parameters fo r the receive sts-3/stm-1 telecom bus interface. 5.3 the transmit sts-3/stm-1 telecom bus interface timing in the transmit sts-3/stm-1 telecom bus interface, all of the signals (which are input via this bus interface) are sampled upon the rising edge of txa_clk (19.44mhz clock signal). figure 21 presents an illustration of the wave forms and the timing parameters (t 13 and t14) of the signals that will be received by the transmit st s-3/stm-1 telecom bus interface. f igure 20. w aveforms of the s ignals that are output via the r eceive sts-3/stm-1 t elecom b us i nterface t able 15: t iming i nformation for the r eceive sts-3/stm-1 t elecom b us i nterface s ymbol d escription m in . t yp . m ax . t 12 rising edge of rxd_clk to updates in rxd_d[7:0], rxd_pl, rxd_c1j1, rxd_alarm and rxd_dp 0ns 3ns t 12 rxd_clk rxd_d[7:0] rxd_pl rxd_c1j1 a2 c1 c1 j1 data j1
xrt94l43 310 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper n ote : the value for t 13 and t 14 can be found in table 16 . table 16 presents information on the timing parameters for the transmit sts-3/stm-1 telecom bus interface. 6.0 transmit toh overhead input port 6.1 transmit toh overhead input port the transmit toh overhead input port permits the user to insert his/her own value for the toh bytes into the outbound sts-12/stm-4 data-stream. the user should note that the txtohins and the txtoh input pins are sampled (by the transmit toh overhe ad input port) upon the ri sing edge of txtohclk. all of the remaining f igure 21. w aveforms of the signals that are input via the t ransmit sts-3/stm-1 t elecom b us i nter - face t able 16: t iming i nformation for the t ransmit sts-3/stm-1 t elecom b us i nterface s ymbol d escription m in . t yp . m ax . t 13 txa_d[7:0], txa_pl, txa_c1j1, txa_alarm and txa_dp to rising edge of txa_clk set-up time requirements 10ns t 14 rising edge of txa_clk to txa_d[7:0], txa_pl, txa_c1j1, txa_alarm and txa_dp hold time requirements 0 ns a2 c1 c1 j1 data data t 13 t 14 txa _c1j1 txa _pl txa _clk txa _d[7:0]
xrt94l43 311 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 signals (e.g., txtohframe and txtohe nable) are updated upon the falling edge of txtohclk. the timing waveform and information for the transmit to h overhead input port is presented below. n ote : the values for t 15 , t 16 and t 17 can be found in table 17 . 7.0 transmit poh overhead input port 7.1 transmit poh o verhead input port the transmit poh overhead input port permits the user to insert his/her own value for the poh bytes into either the outbou nd sts-1 spe data-stream (which is output via the transmit sts-12/stm-4 da ta-stream or via the outbound sts-1 spe data -stream (which is output via the transmit sts- 1 data-stream) . the user should note that the txpohi ns and the txpoh input pins are sample d (by the transmit poh overhead input port) upon the rising edge of txpohclk. all of the remaining signals (e.g., txpohframe and txpohenable) are updated upon the falling edge of txpohclk. the timing waveform a nd information for the transmit poh overhead input port is presented below. f igure 22. t iming w aveform of the t ransmit toh o verhead i nput p ort t able 17: t iming i nformation for the t ransmit toh o verhead i nput p ort s ymbol d escription m in . t yp . m ax . t 15 falling edge of txtohclk to rising edge of txtohframe and txtohenable -0.5ns 0.5ns t 16 txtohins to rising edge of txtohclk set-up time 12ns t 17 txtoh data to rising edge of txtohclk set-up time 11ns txtoh txtohins txtohclk txtohframe txtohenable t 15 t 16 t 17
xrt94l43 312 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper n ote : the values for t 18 , t 19 and t 20 can be found in table 18 . 8.0 transmit orderwire (e1, f1, e2) byte overhead input port 8.1 transmit e1, f1, e2 (order-wire) byte overhead input port the transmit order-wire byte overhead input port provides a dedicated port for the user to insert his/her own value for the e1, f1 and e2 bytes within the outbound st s-12/stm-4 data-stream. the user should note that the txe1f1e2 input pin is sampled (by the transmit or der-wire byte overhead input port) upon the rising edge of txtohclk. all of the remaining signals (e.g ., txe1f1e2enable, txe1f1e2frame) are updated upon the falling edge of txtohclk. th e timing waveform and in formation for the tran smit order-wire byte overhead input port is presented below. f igure 23. t iming w aveform of the t ransmit poh o verhead i nput p ort t able 18: t iming i nformation for the t ransmit poh o verhead i nput p ort s ymbol d escription m in . t yp . m ax . t 18 falling edge of txpohclk to rising edge of txpohframe and txpohenable -1.5ns 3ns t 19 txpohins to rising edge of txpohclk set-up time 15ns t 20 txpoh data to rising edge of txpohclk set-up time 14ns txpoh txpohins txpohclk txpohframe txpohenable t 18 t 19 t 20
xrt94l43 313 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 n ote : the values for t 21 and t 22 can be found in table 19 . 9.0 transmit section dcc insertion input port 9.1 transmit section dcc insertion input port the transmit section dcc insertion input port provides a dedicated port for the user to insert his/her own value for the d1, d2 and d3 bytes within the outbound st s-12/stm-4 data-stream. the user should note that the txsdcc input pin is sa mpled (by the transmit section dcc insertion input port) upon the rising edge of f igure 24. t iming w aveform of the t ransmit o rder -w ire b yte o verhead i nput p ort t able 19: t iming i nformation for the t ransmit o rder -w ire b yte o verhead i nput p ort s ymbol d escription m in . t yp . m ax . t 21 falling edge of txtohclk to rising edge of txe1f1f2enable and txe1f1f2frame -0.5ns 0.5ns t 22 txe1f1f2 data to rising edge of txtohclk set-up time 11ns txe1f1e2 txtohclk txe1f1e2fr txe1f1e2enb t 21 t 22
xrt94l43 314 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper txtohclk. the txsdccenable output signal is upda ted upon the falling edge of txtohclk. the timing waveform and information for the transmit secti on dcc insertion input port is presented below. n ote : the values for t 23 and t 24 can be found in table 20 . 10.0 transmit line dcc insertion input port 10.1 transmit line dcc insertion input port the transmit section dcc insertion input port provides a dedicated port for the user to insert his/her own value for the d4 through d12 bytes within the outbound sts-12/stm-4 data-stream. the user should note that the txldcc input pin is sampled (by the transmit section dcc insertion input port) upon the rising edge f igure 25. t iming w aveform of the t ransmit s ection dcc o verhead i nsertion p ort t able 20: t iming i nformation for the t ransmit o rder -w ire b yte o verhead i nput p ort s ymbol d escription m in . t yp . m ax . t 23 falling edge of txtohclk to rising edge of txsdccenable -0.5ns 0.5ns t 24 txsdcc data to rising edge of txtohclk set-up time 12ns txsdcc txsdccenb txtohclk t 23 t 24
xrt94l43 315 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 of txtohclk. the txldccenable outp ut signal is updated upon the falling edge of txtohclk. the timing waveform and information for the transmit line dcc insertion input port is presented below. n ote : the values for t 25 and t 26 can be found in table 21 . 11.0 receive toh overhead output port 11.1 receive toh over head output port the receive toh overhead output port permits the user to extract out the values of the toh bytes within the incoming sts-12/stm-4 data-stream. all of the rece ive toh overhead output port signals are updated upon f igure 26. t iming w aveform of the t ransmit l ine dcc i nsertion i nput p ort t able 21: t iming i nformation for the t ransmit l ine dcc i nsertion i nput p ort s ymbol d escription m in . t yp . m ax . t 25 falling edge of txtohclk to rising edge of txldccenable -0.5ns 0.5ns t 26 txldcc data to rising edge of txtohclk set-up time 11ns txldcc txldccenb txtohclk t 25 t 26
xrt94l43 316 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper the falling edge of rxtohclk. the timing waveform and information fo r the receive toh overhead output port is presented below. n ote : the values for t 27 and t 28 can be found in table 22 . 12.0 receive poh overhead output port 12.1 receive poh overhead output port the receive poh overhead output port permits the user to extract out the values of the poh bytes within the incoming sts-12/stm-4 data-stream. all of the re ceive poh overhead output port signals are updated upon the falling edge of rxpohclk. the timing waveform and informat ion for the receive poh overhead output port is presented below. f igure 27. t iming w aveform of the r eceive toh o verhead o utput p ort t able 22: t iming i nformation for the r eceive toh o verhead o utput p ort s ymbol d escription m in . t yp . m ax . t 27 falling edge of rxtohclk to rising edge of rxtohframe and rxtohvalid -0.2ns 0.4ns t 28 falling edge of rxtohclk to rxtoh output delay 0.2ns 0.1ns rxtoh rxtohclk rxtohframe rxtohvalid t 27 t 28
xrt94l43 317 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 n ote : the values for t 29 and t 30 can be found in table 23 . 13.0 receive orderwire (e1, f1, e2) bytes overhead output port 13.1 receive e1, f1, e2 (order-wire) byte overhead output port the receive order-wire byte overhead output port provid es a dedicated port for the user to extract out the order-wire (e.g., the e1, f1 and e2) bytes from that within the incoming sts-12/stm-4 data-stream. the user f igure 28. t iming w aveform of the r eceive poh o verhead o utput p ort t able 23: t iming i nformation for the r eceive poh o verhead o utput p ort s ymbol d escription m in . t yp . m ax . t 29 falling edge of rxpohclk to rising edge of rxpohframe and rxpohvalid 0.2ns 3ns t 30 falling edge of rxpohclk to rxpoh output delay 0.2ns 1.5ns rxpoh rxpohclk rxpohframe rxpohvalid t 29 t 30
xrt94l43 318 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper should note that all of th e output signals (of this port) are updated upon the falling edge of rxtohclk. the timing waveform and information fo r the receive order-wire byte overhead output port is presented below. n ote : the values for t 31 and t 32 can be found in table 24 . 14.0 receive section dcc extraction output port 14.1 receive section dcc output port the receive section dcc output port provides a dedicate d port for the user to ex tract out the section dcc (e.g., d1, d2 and d3) bytes from that within the incoming sts-12/stm-4 data-stream. the user should note that all of the output signals (of this port) are updated upon the falling ed ge of rxtohclk. the timing waveform and information for the receive se ction dcc output port is presented below. f igure 29. t iming w aveform of the r eceive o rder -w ire b yte o verhead o utput p ort t able 24: t iming i nformation for the r eceive o rder -w ire b yte o verhead o utput p ort s ymbol d escription m in . t yp . m ax . t 31 falling edge of rxtohclk to rising edge of rxe1f1e2frame and rxe1f1e2valid -0.2ns 0.4ns t 32 falling edge of rxtohclk to rxe1f1e2 output delay 0.1ns 0.3ns rxe1f1e2 rxtohclk rxe1f1e2fr rxe1f1e2val t 31 t 32
xrt94l43 319 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 n ote : the values for t 33 and t 34 can be found in table 25 . 15.0 receive line dcc extraction output port 15.1 receive line dcc output port the receive line dcc output port provides a dedicated po rt for the user to extract out the line dcc (e.g., d4 through d12) bytes from that within t he incoming sts-12/stm-4 data-stream. the user should note that all of the output signals (of this port) are updated u pon the falling edge of rxtohclk . the timing waveform and information for the receive line dcc output port is presented below. f igure 30. t iming w aveform of the r eceive s ection dcc o utput p ort t able 25: t iming i nformation for the r eceive s ection dcc o utput p ort s ymbol d escription m in . t yp . m ax . t 33 falling edge of rxtohclk to rising edge of rxsdccvalid 0ns 0.5ns t 34 falling edge of rxtohclk to rxsdcc output delay 0.1ns 0.5ns rxsdcc rxtohclk rxsdccval t 33 t 34
xrt94l43 320 rev. 1.0.2 sonet/sdh oc-12 to 12xds3/e3 mapper n ote : the values for t 35 and t 36 can be found in table 26 . f igure 31. t iming w aveform of the r eceive l ine dcc o utput p ort t able 26: t iming i nformation for the r eceive l ine dcc o utput p ort s ymbol d escription m in . t yp . m ax . t 35 falling edge of rxtohclk to rising edge of rxldccvalid -0.2ns 0.1ns t 36 falling edge of rxtohclk to rxldcc output delay 0.1ns 0.4ns rxldcc rxtohclk rxldccval t 35 t 36
xrt94l43 321 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 ordering information package dimensions p art n umber p ackage o perating t emperature r ange xrt94l43ib 516 pbga -40 0 c to +85 0 c 516 ball plastic ball grid array (35 x 35 mm pbga) rev. 1.0 (bottom view) a1 c a2 d2 b a symbol millimeters min max inches min max a1 0.028 0.020 a2 0.051 0.039 b 0.035 0.024 d1 1.250bsc c 1.27bsc 0.050bsc 0.70 0.50 1.30 1.00 0.90 0.60 31.75bsc note: the control dimension is the millimeter column d 1.386 1.370 35.20 34.80 0.016 0.028 0.40 0.70 d2 1.185 1.177 30.10 29.90 a 0.106 0.075 2.70 1.90 e a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 26 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 e d1 d b e d1 d chamfer optional
322 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and schedules contai ned here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2006 exar corporation datasheet november 2006. reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. xrt94l43 sonet/sdh oc-12 to 12xds3/e3 mapper rev. 1.0.2 revision history r evision # d ate d escription p1.0.0 july 2002 short form. p1.0.1 july 2002 added pin out and register tables. p1.0.2 august 2002 added descriptive sections. p1.0.3 august 2002 added more description to sections. p1.0.4 september 2002 corrected direct addreses by adding 100hex to each. p1.0.4 december 2002 added sdh register tables and direct addressing pin out. made minor edits to tesxt and broke data sheet into three books, (description and pin outs, sonet registers and sdh registers. p1.0.5 may 2002 added electrical characteristics. 1.0.0 june 2004 final edits, release to production 1.0.1 july 2006 made edits to pin descriptions 1.0.2 november 2006 added/changed block diagrams and features.

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